IC Layout Hotspot Prediction for CMP Recipe Selection

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Solution Overview

Problem

The existing methods for manufacturing integrated circuits are inefficient in detecting and preventing topology hotspots, such as those caused by Chemical Mechanical Polish (CMP) processes, which can lead to defects like circuit shorting or breaking, and require lengthy processes to identify and correct.

Innovation Solution

A hotspot avoidance method that predicts hotspots in integrated circuit manufacturing by using a hotspot library and hash values to identify potential defects, allowing for the selection of an optimal CMP recipe to minimize hotspot occurrence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If physical wafer measurement and manual inspection methods are used to detect topology hotspots, then measurement precision can be maintained, but manufacturing time increases significantly (taking three months) and productivity decreases

Engineering Contradiction:
Improvehotspot detection precisionVSAvoidmanufacturing cycle time
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent creates a virtual model (copy) of the physical wafer topology using layout data and process parameters. This virtual model allows hotspot prediction through simulation rather than physical measurement, dramatically reducing detection time while maintaining precision. The virtual wafer model includes topological features that can be analyzed computationally to predict CMP hotspots before actual manufacturing.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent performs hotspot prediction and recipe optimization in advance, before actual wafer manufacturing. By using the virtual model to predict hotspots and determine optimal CMP recipes beforehand, the system prevents defects rather than detecting them after manufacturing, thus reducing overall manufacturing cycle time while maintaining quality.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple process phases (circuit design, layout, manufacturing, measurement) are performed sequentially to identify topology defects, then comprehensive defect detection is achieved, but the process duration extends to three months

Engineering Contradiction:
Improvedefect detection completenessVSAvoidprocess duration
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent introduces a virtual model as an intermediary between circuit layout and physical manufacturing. This virtual model allows topology analysis and hotspot prediction to be performed computationally without requiring actual physical manufacturing and measurement, thus eliminating the need for sequential process phases while maintaining comprehensive defect detection capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the mechanical/physical measurement system with a computational simulation system. Instead of physically manufacturing wafers and measuring them with equipment, the system uses computer-based virtual modeling and algorithmic analysis to predict hotspots, substituting physical processes with digital ones to reduce time while maintaining detection reliability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Ease of manufacture

If standard CMP processes are used without hotspot prediction, then manufacturing simplicity is maintained, but topology hotspots occur leading to circuit defects

Engineering Contradiction:
Improveprocess simplicityVSAvoidtopology defect rate
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent performs preliminary hotspot prediction and recipe optimization before actual CMP manufacturing. By analyzing the virtual model to identify potential hotspots and determining optimal CMP recipes in advance, the system prevents topology defects without adding complexity to the actual manufacturing process. The optimal recipe is then applied directly during standard CMP operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses the circuit layout data and process parameters that are already available to automatically generate the virtual model and predict hotspots. The same process parameters used in manufacturing serve as input for the prediction system, allowing the system to self-service without requiring additional external data or complex integrated workflows.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12229487B2Hotspot avoidance method of manufacturing integrated circuits
Publication Date: 2025.02.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12229487B2 patent drawing
  • US12229487B2 patent drawing
  • US12229487B2 patent drawing

AI summary

A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.