IC Interconnect Layout With Sub-1:1 M1 Pitch for Routing Access
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Solution Overview
Problem
In advanced integrated circuit nodes, the rectangular shape of connection pins and the one-to-one ratio of M1 track pitch to polysilicon line pitch limit the availability of routing resources and restrict the placement of device cells under power lines.
Innovation Solution
The integrated circuit structure design reduces the M1 pitch to polysilicon line pitch ratio to less than 1:1, allowing M1 lines to be placed on M1 tracks and increasing routing resources by moving connection pins to the M0 layer, which enables device cells to be placed under M1 power straps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the M1 track pitch is set to match the polysilicon line pitch (1:1 ratio), then all connection pins can be located on the M1 interconnection layer, but the M1 pitch is enlarged and routing resources are reduced
Solution Approach 1:
The patent introduces a second metal interconnection layer (M2) above the first metal interconnection layer (M1) to provide additional routing resources. This multi-layer approach allows connection pins to be distributed across multiple layers, thereby increasing the overall routing capacity without enlarging the M1 pitch and maintaining manufacturing simplicity.
2Ease of operation
If all connection pins are located on the M1 interconnection layer, then pin access is simplified, but device cells cannot be placed directly under power lines formed in the M1 layer
Solution Approach 1:
The patent utilizes the vertical dimension by introducing a second metal interconnection layer (M2) above the first metal interconnection layer (M1). This allows power lines to be formed in the M1 layer while connection pins are accessed through the M2 layer, enabling device cells to be placed directly under power lines without compromising pin access.
3Ease of manufacture
If the M1 pitch is enlarged to match polysilicon line pitch, then connection pins can be located on M1 tracks, but the amount of routing resources in the M1 interconnection layer is reduced
Solution Approach 1:
The patent compensates for the reduced routing capacity in the M1 layer by introducing a second metal interconnection layer (M2). This vertical expansion of the interconnection system restores and enhances overall routing capacity while maintaining the simplified track alignment achieved by matching M1 pitch to polysilicon line pitch.
Data Source
AI summary
An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.