IC Layout Placeholders for Parallel Circuit Macro Integration
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Solution Overview
Problem
IC design complexity and the need for parallel integration of circuit macros pose challenges due to the lengthy development time of these components, leading to delays in the overall IC design cycle.
Innovation Solution
The use of black boxes as placeholders for circuit macros, connected by a connectivity network and supplemented with dummy patterns, allows for parallel design tasks such as connectivity and pattern insertion, enabling the IC design cycle to proceed without waiting for the macros to be fully developed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If circuit macros are integrated into an IC with increased design complexity, then the IC functionality is improved, but the design cycle time is extended
Solution Approach 1:
The patent applies preliminary action by creating placeholder blocks that represent circuit macros before the macros are fully designed. This allows the IC layout design, connectivity planning, and dummy pattern insertion to proceed in parallel with the macro development, rather than waiting sequentially. The placeholder blocks enable early preparation of the overall IC architecture while preserving the ability to integrate the actual macros later.
2Productivity
If multiple circuit macros are developed in parallel to shorten the IC design cycle, then the productivity is improved, but the integration complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the IC design into independent segments: placeholder block creation, connectivity network design, dummy pattern insertion, and actual macro integration. This segmentation allows different teams to work on different aspects simultaneously without interfering with each other, reducing the integration complexity while maintaining parallel development productivity.
3Manufacturing precision
If the IC layout design waits for circuit macros to be fully developed, then the integration accuracy is improved, but the time-to-market is extended
Solution Approach 1:
The patent uses placeholder blocks as intermediaries between the IC layout design process and the actual circuit macros. These placeholders serve as temporary representations that enable the layout design to proceed without the final macro designs, while maintaining the ability to achieve accurate integration later when the actual macros are ready. This intermediary approach preserves integration accuracy while eliminating time delays.
Data Source
AI summary
A method for making an integrated circuit (IC) includes inserting black boxes into a layout of the IC; connecting the black boxes with a connectivity network; and inserting first dummy patterns in areas of the layout outside of the black boxes and the connectivity network. After the inserting of the first dummy patterns, the method further includes replacing the black boxes with circuit macros that have one-to-one correspondence with the black boxes, wherein each of the circuit macros includes circuit patterns in a central area of the respective circuit macro and second dummy patterns surrounding the central area. In the method, at least one of the following operations is performed by an electronic design automation (EDA) tool: the inserting of the black boxes, the connecting of the black boxes, the inserting of the first dummy patterns, and the replacing of the black boxes with the circuit macros.