IC Layout Mark Pattern Fragmentation for Wider Process Windows
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Solution Overview
Problem
The increasing complexity of IC manufacturing processes due to reduced process windows and uneven pattern densities in IC fabrication, particularly in advanced technology nodes, leads to challenges in achieving high fabrication quality and efficiency.
Innovation Solution
A method for modifying IC layouts by dividing mark patterns into subsets and applying double or multiple patterning techniques to adjust feature orientations and densities, enhancing the process window and improving lithography resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dimensions are reduced to improve production efficiency and lower costs, then manufacturing productivity increases, but manufacturing precision deteriorates due to increased process complexity and reduced process windows
Solution Approach 1:
The patent applies segmentation by dividing the mark pattern into multiple subsets and using multiple patterning techniques to form features. This breaks down the complex single-step patterning into sequential steps, allowing each step to be optimized independently for precision while maintaining overall productivity benefits of reduced dimensions
Solution Approach 2:
The patent introduces an additional dimension of control by adjusting feature orientations and densities in the layout design. By modifying the spatial arrangement and orientation of features before fabrication, the process compensates for scaling effects and maintains manufacturing precision at reduced dimensions
2Length of moving object
If IC dimensions are reduced to meet demands for smaller devices, then device size decreases, but process window reduces making fabrication more difficult
Solution Approach 1:
The patent applies dynamics by providing tuning freedom in the layout design process. The feature orientations and densities can be dynamically adjusted during layout modification to optimize the process window for specific fabrication conditions, allowing adaptation to varying manufacturing parameters while maintaining reduced feature sizes
3Reliability
If mark patterns are used in IC layouts for identification, then device functionality is maintained, but uneven pattern densities create fabrication challenges
Solution Approach 1:
The patent applies local quality by modifying pattern density locally in different regions of the IC layout. The mark pattern subsets are arranged with adjusted densities to match local fabrication requirements, ensuring that identification functionality is preserved while local density variations are optimized for uniform fabrication quality across the entire device
Data Source
AI summary
The present disclosure provides a method that includes receiving a circuit layout that includes circuit features and a mark pattern to be formed on a same material layer over an integrated circuit (IC) substrate, the circuit features being longitudinally oriented along a first direction and being distanced from each other along a second direction that is orthogonal to the first direction; fragmenting the mark pattern to generate a fragmented mark pattern having fragmented mark features such that the fragmented mark features are configured in parallel and are longitudinally oriented along a third direction; and generating a modified circuit layout for circuit fabrication, the modified circuit layout including the circuit features and the fragmented mark pattern.