IC Layout Migration via Electrical Patterning
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Solution Overview
Problem
Current IC design methodologies face challenges in effectively migrating designs between technology nodes due to independent processing modules, lack of cross-team interaction, and reduced design flexibility, leading to inefficiencies in manufacturing and performance optimization.
Innovation Solution
The implementation of an electrical patterning (ePatterning) technique that modifies and optimizes IC design layouts to enhance both optical and electrical performance, allowing for seamless migration to new technology nodes while maintaining device performance and architecture, through processes like shrinking, gridding, and compaction, and incorporating OPC features for multi-object optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If independent processing modules are used for lithography patterning, thin film deposition, etching, etc., then each module can be optimized independently, but cross-team interaction is lacking and modeling efficiency is reduced
Solution Approach 1:
The patent merges multiple independent processing modules (lithography patterning, thin film deposition, etching, etc.) into an integrated design flow where all modules interact through a unified platform. This integration enables cross-team collaboration and improves overall modeling efficiency while maintaining the optimization capabilities of individual modules.
2Reliability
If statistical corner is used for design reference, then design can be referenced, but design flexibility and design margin are reduced
Solution Approach 1:
The patent employs parameter changes by allowing dynamic adjustment of design parameters beyond fixed statistical corners. This enables designers to explore multiple design scenarios and maintain flexibility while achieving accurate design references through comprehensive parameter exploration and optimization.
3Reliability
If full chip tape out is required without maximized modeling efficiency, then complete design product is achieved, but development time and cost increase
Solution Approach 1:
The patent applies preliminary action by performing comprehensive modeling and simulation before final tape out. This enables identification and resolution of design issues early in the process, ensuring complete design products are achieved with reduced development time and cost through proactive rather than reactive problem solving.
4Adaptability or versatility
If designer and manufacturer interactions are required for technology node migration, then design can be adapted, but numerous interactions increase complexity and time
Solution Approach 1:
The patent introduces an intermediary automated migration platform that facilitates technology node transitions. This intermediary system handles the complexity of interactions between designers and manufacturers, enabling smooth technology node migrations while reducing direct interaction complexity and time requirements.
Data Source
AI summary
The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.