Mismatch Verification for IC Layout Regions
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Solution Overview
Problem
Integrated circuits designed to perform similarly often exhibit unacceptable mismatches in electrical performance due to variations in placement and routing, despite matching mask layer shapes and compliance with design rules.
Innovation Solution
An integrated circuit design system that includes a selector module to identify regions of interest and a comparator module to evaluate desired characteristics, determining if differences between instantiations are within acceptable tolerances to ensure matched performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If mask layer shapes are matched and design rules are complied with, then manufacturing precision is improved, but electrical performance matching deteriorates
Solution Approach 1:
The patent applies preliminary action by performing mismatch analysis during the design stage before fabrication. The system identifies potential electrical performance mismatches by analyzing layout geometries, proximity effects, and process variation sensitivities, then adjusts the design to prevent mismatches before they occur in the manufactured devices.
Solution Approach 2:
The patent replaces physical electrical measurement and testing with a computational model-based analysis system. Instead of measuring actual electrical performance after fabrication, the system uses process models, layout extraction, and simulation to predict and analyze mismatch characteristics during the design phase, substituting mechanical/electrical measurement with information processing.
2Reliability
If device placement and routing are made identical, then electrical performance matching is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by analyzing and adjusting specific local layout features that contribute to mismatch, such as proximity to active areas, interconnect routing patterns, and local density variations. Instead of requiring global identity of placement and routing, the system identifies and optimizes only the critical local features that affect electrical performance matching.
Solution Approach 2:
The patent uses parameter changes by modifying layout parameters such as spacing, orientation, and positioning of devices and interconnects to achieve better electrical performance matching. The system adjusts geometric parameters of the layout to compensate for process variations and environmental effects, thereby improving mismatch characteristics without requiring identical placement and routing.
Data Source
AI summary
A method can include identifying a device design comprising first and second instantiations of a device, identifying a layer of the device design, identifying a first region of the device design for the first instantiation based on the layer of the first instantiation, and a second region of the device design for the second instantiation based on the layer of the second instantiation. identifying a first compare layer of the device design that comprises a plurality of first compare features including a first compared feature within the first region and a second compared feature within the second region, determining a difference between the first compared feature and the second compared feature, and determining if the difference meets a tolerance to determine if the first instantiation matches the second instantiation.