IC Layout Modification Using Supplemental Photomasks
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Solution Overview
Problem
IC designers face the challenge of incorporating improvements in standard cell designs into existing integrated circuits without access to the original Verilog code or requiring changes to the existing photomask set, as modern design processes rely on modular components and continuous enhancements in cell libraries.
Innovation Solution
A system and method that allow for modifying an IC layout by adding one or more photomasks to replace a subset of transistors with newer versions, differing in characteristics like gate insulation layer thickness, source/drain implant dosage, or gate length, without changing the original photomask set, using commercially available EDA tools and SPICE level models to achieve improved performance or reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the original photomask set is used without modification, then the existing IC layout can be fabricated, but the design cannot take advantage of improved standard cell designs developed after tapeout
Solution Approach 1:
The solution segments the photomask set into two parts: the original photomask set that remains unchanged, and a supplemental photomask that contains only the specific modifications needed. This allows the design to incorporate improved standard cell designs while keeping the modification scope minimal and manageable.
Solution Approach 2:
Instead of redesigning the entire photomask set, the solution applies partial action by creating a supplemental photomask that only covers the specific standard cells that need improvement. This selective approach reduces complexity while achieving the desired adaptability.
2Reliability
If the entire IC layout is redesigned to use improved standard cells, then the design can benefit from newer cell characteristics, but the cost and time required increases significantly
Solution Approach 1:
The solution extracts only the specific standard cells that need improvement and applies the supplemental photomask only to those instances. This allows the design to benefit from newer cell characteristics in critical areas while avoiding the time-consuming process of redesigning the entire IC layout.
Solution Approach 2:
The supplemental photomask applies local quality changes to specific regions of the IC layout where improved standard cells are needed, rather than uniformly modifying the entire design. This targeted approach reduces redesign time while maintaining reliability improvements where they are most needed.
3Ease of operation
If access to the original Verilog code is required to modify the layout, then precise control over cell replacement is possible, but the process becomes more complex and restrictive
Solution Approach 1:
The solution uses copying by creating a supplemental photomask that replicates the modification pattern across multiple instances of the same standard cell type. This allows precise control over which cells are replaced without requiring access to the original Verilog code, simplifying the modification process while maintaining accuracy.
4Adaptability or versatility
If a new photomask set is created to incorporate improved standard cells, then the design can be updated, but the existing photomask set must be changed
Solution Approach 1:
The solution merges the original photomask set with a supplemental photomask during the fabrication process. The supplemental photomask is applied in conjunction with the original set, allowing the design to use improved standard cells while maintaining compatibility with existing fabrication processes and equipment.
Data Source
AI summary
A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.


