IC Layout Enhancement Using Inter-Cell OPC Correlation
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Solution Overview
Problem
The increasing complexity and density of integrated circuits (ICs) in advanced semiconductor technologies have made design and fabrication challenging, with existing lithography enhancement methods like optical proximity correction (OPC) requiring significant resources and time, especially in extreme ultraviolet lithography (EUVL), where diffraction and interference effects are pronounced, leading to inefficiencies and increased costs.
Innovation Solution
A simplified EUVL enhancement framework that includes a training phase to build an enhancement model considering inter-cell correlations, using machine learning to predict lithography results for cells based on a reference cell, reducing the need for individual optimization of each cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical proximity correction is performed repeatedly across the design layout to ensure acceptable enhancement results, then lithography enhancement quality is improved, but software resource consumption and processing time increase significantly
Solution Approach 1:
The patent applies copying by training a neural network model on a subset of design layout data and then using the trained model to predict enhancement results for the entire design layout. This eliminates the need to repeatedly perform computationally intensive optical proximity correction across all patterns, while still achieving acceptable enhancement quality through the learned correlations from the training phase.
2Manufacturing precision
If optical proximity correction is performed repeatedly across the design layout to ensure acceptable enhancement results, then lithography enhancement quality is improved, but processing cost increases significantly
Solution Approach 1:
The patent applies copying by training a neural network model on a subset of design layout data and then using the trained model to predict enhancement results for the entire design layout. This eliminates the need to repeatedly perform computationally intensive optical proximity correction across all patterns, while still achieving acceptable enhancement quality through the learned correlations from the training phase.
3Adaptability or versatility
If design complexity and device density continue to increase, then circuit functionality is improved, but design cycle time increases
Solution Approach 1:
The patent applies preliminary action by performing the computationally intensive neural network training phase on a representative subset of design layout data before finalization. This preliminary training captures the essential correlations and patterns, allowing rapid prediction and enhancement of the complete design layout afterward, thereby reducing overall design cycle time while handling increased circuit complexity and device density.
Data Source
AI summary
A method includes: providing a first design layout including a plurality of cells; updating a first cell of the plurality of cells using optical proximity correction to provide a first updated cell and a data set; and updating a second cell from remaining cells in the first design layout based on the data set and a model without involvement of optical proximity correction to provide a second updated cell, wherein the model includes hidden layers including nodes and is trained to obtaining converged values of the nodes of the hidden layers through providing a mapping of edge segments before lithography enhancement and edge segments after lithography enhancement using optical proximity correction, and wherein at least one of the providing, and updating is executed by one or more processors.