IC Layout Verification Using Parallel Window Splitting
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Solution Overview
Problem
Modern integrated circuit (IC) design is complex and requires efficient automated tools for physical verification, particularly in handling parasitic capacitance and resistance structures, while ensuring rapid design and manufacturing compliance with numerous rules and statistical manufacturing unpredictability.
Innovation Solution
A system and method for physical verification workflow that includes extraction of parasitic capacitance and resistance structures, automatic splitting of IC layout for parallel processing, and use of a metadata matrix to minimize resources for generating IC masks, implemented in single-host-multi-core or cloud-based environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If automated design tools are used for physical verification, then verification accuracy is improved, but computational resources and processing time increase
Solution Approach 1:
The IC layout is automatically split into multiple sections or regions, allowing the verification process to be divided into smaller parallel tasks. Each section can be processed independently, reducing the computational burden on single resources while maintaining overall verification accuracy through coordinated processing of all sections.
2Measurement precision
If automated design tools are used for physical verification, then verification accuracy is improved, but processing time increases
Solution Approach 1:
The layout splitting enables parallel processing of different IC sections simultaneously, reducing total processing time while maintaining verification accuracy through comprehensive checking of all segments.
Solution Approach 2:
The system performs preliminary analysis to identify and extract parasitic capacitance and resistance structures before the main verification process. This preparatory extraction organizes data in advance, allowing the subsequent verification to proceed more efficiently with pre-processed information.
3Manufacturing precision
If detailed parasitic extraction is performed, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The system automatically extracts and identifies parasitic capacitance and resistance structures in advance, organizing this complex information into structured data formats. This preliminary extraction simplifies the subsequent verification process by having parasitic data ready in an organized manner, reducing the apparent complexity during main verification.
Solution Approach 2:
The system introduces intermediate data structures and metadata to bridge the complex parasitic extraction process and the verification process. These intermediaries organize and manage the complex parasitic data, making it more manageable and reducing the effective complexity of the overall system.
4Productivity
If metadata matrix is used to minimize information volume, then productivity is improved, but measurement precision may be reduced
Solution Approach 1:
The system transforms detailed parasitic extraction data into a compressed metadata matrix format that retains essential verification information while reducing data volume. This parameter transformation maintains critical precision by preserving key electrical characteristics in a more efficient representation, enabling both high productivity and adequate measurement precision.
Data Source
AI summary
An electronic design automation (EDA) tool and system for physical verification of workflow for semiconductor circuit designs, and methods of using the same is described. Generally, the method includes (i) automatic splitting an integrated circuit (IC) layout into a number of windows for parallel processing using a plurality of central processing cores; (ii) extracting parasitic capacitance structures from the IC layout; (iii) generating fill elements for masks to fabricate an IC having the IC layout using a metadata matrix to minimize volume of information and resources needed; and (iv) extraction of parasitic resistance structures from IC layout. In some embodiments, the IC layout is additionally or alternatively split into groups of rules for processing. Other embodiments are also described.