IC Layout Tiling for Accurate Parasitic Extraction
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Solution Overview
Problem
Existing parasitic extraction tools struggle to accurately calculate parasitic effects in IC designs with omni-directional and curvilinear interconnects due to high computational burden and memory consumption, especially when dealing with large designs and manufacturing non-idealities.
Innovation Solution
A layout verification tool divides the IC design layout into tiles and uses a solver to compute parasitic values for interconnect segments within neighboring tiles, employing field solvers or machine-trained networks to calculate self-capacitance and capacitive coupling, applicable to both omni-directional and Manhattan designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If field solvers are used to compute parasitic values for omni-directional and curvilinear interconnects, then measurement precision is improved, but productivity deteriorates due to high computational burden and memory consumption
Solution Approach 1:
The layout is divided into multiple tiles, and the interconnects are segmented at tile boundaries. This allows the field solver to process smaller segments independently rather than the entire layout at once, reducing computational burden and memory consumption while maintaining accuracy for each segment
Solution Approach 2:
The patent introduces a tile-based spatial organization that adds a hierarchical dimension to the extraction process. By organizing segments into tiles and processing them in a hierarchical manner (within-tile then between-tile), the solution manages computational complexity without sacrificing precision
2Measurement precision
If smaller panels are included in the input data to improve accuracy, then measurement precision is improved, but loss of time and loss of substance worsen due to increased run-time and memory usage
Solution Approach 1:
The layout is divided into multiple tiles, and the interconnects are segmented at tile boundaries. This allows the field solver to process smaller segments independently rather than the entire layout at once, reducing computational burden and memory consumption while maintaining accuracy for each segment
Solution Approach 2:
The patent computes parasitic values for segments within tiles and then combines them with adjustments for between-tile effects. This partial computation approach avoids processing the entire layout with full detail everywhere, reducing runtime while maintaining necessary accuracy through the combination step
3Productivity
If approximate solutions using pattern matching techniques are used, then productivity is improved, but measurement precision deteriorates for omni-directional and curvilinear designs
Solution Approach 1:
By segmenting interconnects into smaller sections and computing parasitic values for each segment, the patent enables the use of field solvers on manageable portions of the layout. This segmentation makes it feasible to apply accurate field-based methods to larger designs than previously possible
Solution Approach 2:
The patent changes the approach from using fixed pattern-matching templates to computing parasitic values based on actual segment geometry and position. This parameter-based computation adapts to omni-directional and curvilinear interconnects, improving precision while maintaining reasonable productivity through the segmented approach
4Measurement precision
If the entire layout is processed as a single unit, then measurement precision is improved, but device complexity worsens due to memory consumption requirements
Solution Approach 1:
The layout is divided into multiple tiles, and the interconnects are segmented at tile boundaries. This allows the field solver to process smaller segments independently rather than the entire layout at once, reducing computational burden and memory consumption while maintaining accuracy for each segment
Solution Approach 2:
The patent combines the parasitic values computed for individual segments with adjustments for between-tile effects to produce the overall parasitic parameters. This merging step integrates the segmented results into a complete solution without requiring the entire layout to be held in memory simultaneously
Data Source
AI summary
Some embodiments provide a method for calculating parasitics for an IC design layout that on at least one layer includes neighboring interconnects that are neither parallel nor perpendicular to each other. The method divides the layout into tiles such that each of a set of interconnects is divided into segments each of which is located in a respective tile. Each tile of a set of the tiles includes two or more segments that are neither parallel nor perpendicular. For each segment located in a tile, the method uses a parasitic value solver to compute a set of parasitic values representing parasitic effects exerted on the segment by a set of other segments in the tile and a set of neighboring tiles. For each interconnect, the method computes a set of overall parasitic values based on the parasitic values computed for the segments of the interconnect.