IC Layout Partitioning for Manufacturability
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Solution Overview
Problem
The semiconductor manufacturing industry faces challenges in achieving balanced IC design rules that enhance manufacturability without disrupting established design flows, as conventional global design rules struggle with sub-wavelength photolithography, leading to manufacturability issues and reduced yield due to aggressive design requirements.
Innovation Solution
A back-end methodology that applies localized design rules and resolution enhancement techniques (RET) to specific areas of the IC layout, optimizing manufacturability by partitioning the design into granular levels and adjusting rules based on critical layout properties, thereby minimizing global process tolerance and maximizing design density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If aggressive global design rules are applied to achieve tighter IC designs, then design density is improved, but manufacturability deteriorates due to sub-wavelength photolithography limitations
Solution Approach 1:
The patent applies different design rules locally to specific pattern instances rather than using uniform global rules. The system identifies difficult-to-manufacture patterns and applies relaxed design rules only to those specific locations, while maintaining aggressive rules for other areas. This localized approach preserves overall design density while improving manufacturability of critical patterns.
Solution Approach 2:
The system dynamically adjusts design rule parameters based on the specific characteristics of each pattern instance. By analyzing pattern complexity and manufacturing difficulty, the system modifies parameters such as minimum feature size and spacing requirements locally, transforming the rigid global design rule approach into a flexible, adaptive system that balances density and manufacturability.
2Ease of manufacture
If global design rules are relaxed to improve manufacturability, then ease of manufacture is improved, but design density deteriorates
Solution Approach 1:
Instead of relaxing design rules globally, the system identifies specific pattern instances that require relaxed rules for manufacturability. By applying rule modifications only to those localized areas with manufacturing difficulties, the system maintains high design density in the overall design while ensuring manufacturability of critical patterns.
3Reliability
If localized design rules and RET are applied to optimize manufacturability, then yield is improved, but device complexity increases due to partitioning and rule adjustment
Solution Approach 1:
The patent segments the IC design into multiple pattern instances and applies design rules selectively to each segment. The system partitions the design layout to identify difficult patterns and applies appropriate design rules and RET techniques to each segment, improving yield through targeted optimization while managing complexity through systematic segmentation.
Solution Approach 2:
The system automatically analyzes pattern instances, identifies manufacturing difficulties, and applies appropriate design rules and RET techniques without requiring manual intervention for each pattern. This self-service approach improves yield through comprehensive analysis while minimizing the increase in design process complexity by automating the rule application process.
Data Source
AI summary
A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.