IC Layout Pattern Correction for Automated ECO Constraint Compliance
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Solution Overview
Problem
Current semiconductor IC design methods face challenges in automated engineering change orders (ECOs) that often violate manufacturing constraints, lead to costly manual modifications, and fail to converge to feasible solutions, affecting timing and signal integrity.
Innovation Solution
A method and apparatus for determining a second pattern of an IC design by identifying sets of design connections based on routes, selecting pre-determined routes, and modifying the design to improve compliance with manufacturing constraints, using a processor to route and compact the layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated ECO methods are used to modify IC design, then design modification speed is improved, but manufacturing constraint violations increase
Solution Approach 1:
The system performs preliminary actions by identifying and grouping design connections into sets before route modification, and by using pre-determined routes that are预先 validated to meet manufacturing constraints. This preliminary organization prevents constraint violations during automated ECO execution.
Solution Approach 2:
The patent introduces an intermediary mechanism - the design connection sets and pre-determined routes - that mediate between the automated ECO modification process and manufacturing constraints. This intermediary layer ensures that automated modifications adhere to constraints without requiring manual intervention.
2Manufacturing precision
If manual modification is used to correct manufacturing constraints, then manufacturing constraint compliance is improved, but time consumption and cost increase
Solution Approach 1:
The system enables self-service by automatically identifying design connections, grouping them into sets, and selecting appropriate pre-determined routes without manual intervention. The automated ECO process serves itself by incorporating manufacturing constraint compliance directly into the automated workflow, eliminating the need for costly and time-consuming manual corrections.
3Adaptability or versatility
If automated ECO modifies or displaces standard-cells, then design adaptability is improved, but manufacturing constraint violations increase
Solution Approach 1:
The patent applies local quality by treating different design connections and standard-cell modifications locally through specific sets and pre-determined routes. Each modification is handled according to its specific characteristics and constraints, allowing adaptability while maintaining local manufacturing constraint compliance.
4Productivity
If automated ECO is used to increase feature density, then productivity is improved, but convergence to feasible solution decreases
Solution Approach 1:
The system performs preliminary actions by organizing design connections into sets and preparing pre-determined routes before attempting to increase feature density. This preliminary structure provides a reliable foundation that guides the density improvement process toward feasible solutions, enhancing convergence reliability.
Data Source
AI summary
A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.