IC Layout Pattern Detection via Topological Relations
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Solution Overview
Problem
Current methods for checking integrated circuit layouts for complex patterns are not user-friendly, as they require complex formal definitions and are difficult to maintain, especially for patterns that cannot be described using existing tools like SVRF, leading to manufacturability issues due to the inability to detect variations in geometrically described patterns.
Innovation Solution
A method that allows users to draw a reference pattern intuitively, deducing a basic pattern definition and set of topological relations, which are then used to form a complex pattern description for checking the layout, enabling the detection of instances of the pattern without requiring detailed formal knowledge, and providing feedback and user input options for adapting the relations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If exact geometric copying is used for pattern detection, then manufacturing precision is improved, but adaptability deteriorates because only identical patterns are detected
Solution Approach 1:
The patent changes the detection parameters from exact geometric matching to topological relationship matching. Instead of requiring identical coordinates and dimensions, the system detects patterns based on topological relations (adjacency, connectivity, spatial relationships) that remain invariant under geometric transformations. This allows detection of pattern variations while maintaining manufacturing precision.
Solution Approach 2:
The patent inverts the approach by not trying to match the query pattern against all possible geometric variations, but rather defining the pattern through its essential topological properties and letting the detection algorithm find instances that satisfy these properties regardless of specific geometric parameters.
2Measurement precision
If complex formal definitions are used for pattern specification, then measurement precision is improved, but ease of operation deteriorates
Solution Approach 1:
The patent introduces an intermediary layer between the user and the complex detection algorithms. The user interacts with a simplified graphical interface to draw patterns, while the system automatically converts these drawings into topological relationship definitions and executes the detection. This intermediary interface hides the complexity of topological logic from the user.
Solution Approach 2:
The system performs automatic conversion of user drawings into formal topological definitions without requiring user input of complex parameters. The pattern detection algorithm automatically extracts topological relationships from the drawn pattern and uses these for detection, making the process self-serve and eliminating the need for users to understand complex specification languages.
3Manufacturing precision
If SVRF with algorithms is used for design rule specification, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the essential topological relationships from complex SVRF algorithms and uses only these extracted relationships for pattern detection. By separating the essential topological logic from the complex algorithmic overhead, the system achieves design rule enforcement with reduced complexity.
Data Source
AI summary
A method 100, a computer program product and a system of checking an integrated circuit layout for instances of a reference pattern is provided The method 100 comprises the steps of: i) receiving 102 the integrated circuit layout, ii) receiving 104 a drawing of the reference pattern from a user, iii) deducting 106 a basic pattern definition from the drawn reference pattern, iv) determining 108 a set of topological relation based on the drawn reference pattern, v) forming 110 a complex pattern description which is a combination of the deducted basic pattern definition and the set of topological relations, vi) checking 112 the integrated circuit layout for patterns that match the complex pattern description to find instances of the reference pattern in the integrated circuit layout, and vii) storing 114 found instances of the reference pattern.