Integrated Circuit Layout Pattern Merging for Mask Reduction
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Solution Overview
Problem
The existing semiconductor IC design processes require multiple masks for forming certain patterns, leading to increased manufacturing costs and complexity, especially as the number of masks necessary for forming specific layers exceeds a threshold, causing issues with patterning resolution and color conflicts during the placement and routing of standard cells.
Innovation Solution
A method is introduced to modify the IC layout by merging or connecting patterns to reduce the number of masks needed, involving design polishing techniques such as optical proximity correction (OPC) and pattern merging or bridge pattern addition, allowing for the formation of new patterns using fewer masks, thereby reducing manufacturing costs and improving design efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used for forming patterns in IC layout, then pattern formation capability is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent merges multiple separate patterns into a single combined pattern that can be formed using fewer masks. Specifically, it combines first and second patterns into a third pattern, reducing the total number of masks required while maintaining the ability to form all necessary patterns in the IC layout.
Solution Approach 2:
The combined pattern serves multiple functions simultaneously - it forms both the first and second patterns that would traditionally require separate masks. This multi-functionality reduces the overall mask count while preserving pattern formation capabilities for different IC components.
2Ease of manufacture
If the number of masks is reduced, then manufacturing cost decreases, but patterning resolution may be compromised
Solution Approach 1:
The patent segments the combined pattern into distinct first and second patterns through strategic placement of pattern elements. By separating the combined pattern into identifiable segments, it ensures that each original pattern can be formed with appropriate resolution while being created through a single mask operation.
Solution Approach 2:
The combined pattern acts as an intermediary that bridges the gap between reduced mask count and maintained resolution. It serves as a middleman that allows fewer masks to be used while still achieving the necessary patterning precision through careful design of the combined pattern geometry.
3Adaptability or versatility
If patterns are merged to reduce mask count, then design flexibility improves, but layout complexity increases
Solution Approach 1:
The patent introduces dynamic adjustability in the layout by allowing the combined pattern to be configured in different arrangements. The first and second patterns can be positioned in various relative locations within the combined pattern, enabling flexible adaptation to different IC design requirements while maintaining reduced mask count.
Solution Approach 2:
The patent applies different design qualities to different regions of the combined pattern. By strategically placing the first and second patterns in specific locations within the combined pattern, it optimizes local characteristics to match different functional requirements of the IC while maintaining overall simplicity.
Data Source
AI summary
A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.