IC Design Layout Post-Layout Enhancement via GDS Stream Analysis
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Solution Overview
Problem
Current IC design verification processes are computationally intensive and do not allow for post-layout enhancements, such as inserting redundant vertical interconnect accesses (VIAs) or shape modifications, due to their focus on pre-mask data preparation, which limits manufacturability and yield optimization.
Innovation Solution
A method and apparatus that receive a data stream of an integrated circuit design layout, perform manufacturability and yield-enhancement analysis, determine design constructs, and transmit router-specific directives back to the design stage for implementing enhancements, including new layout features and VIAs, to optimize layout density, printability, and critical-area effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If design verification processes focus on pre-mask data preparation, then design rule checking can be performed, but post-layout enhancements such as inserting redundant VIAs or shape modifications are not possible
Solution Approach 1:
The patent inverts the traditional design verification sequence by performing manufacturability analysis after GDS stream-out and then feeding recommendations back to the design stage. This reverse approach enables post-layout enhancements (like adding redundant VIAs and shape modifications) to be implemented while still improving manufacturability and yield, rather than being constrained by pre-mask verification limitations
2Reliability
If design verification techniques are executed on a single processing platform, then design rule checking can be performed, but the process requires several days to weeks to generate results
Solution Approach 1:
The patent segments the design verification process into distinct phases: (1) GDS stream-out with manufacturing format conversion, (2) manufacturability analysis on a separate processing platform, (3) extraction of design constructs, and (4) feedback to the design stage. This segmentation enables parallel processing and significantly reduces design cycle time while maintaining verification accuracy
Solution Approach 2:
The patent introduces an intermediary processing platform that receives GDS streams, performs manufacturability analysis, and generates design construct recommendations. This intermediary layer acts as a bridge between the design stage and manufacturing, enabling efficient analysis without burdening the original design verification platform and reducing overall processing time
3Manufacturing precision
If layout data size quadruples with every technology node, then manufacturing precision requirements increase, but computational scalability of enhancement techniques deteriorates
Solution Approach 1:
The patent extracts only the essential design constructs and manufacturability recommendations from the comprehensive GDS stream analysis, rather than processing the entire large-scale layout data. This extraction approach maintains manufacturing precision by identifying critical features while reducing computational complexity by focusing analysis on key manufacturability factors rather than all layout elements
Data Source
AI summary
An approach is provided for applying post graphic data system (GDS) stream enhancements back to the design stage. Embodiments include receiving a data stream of an integrated circuit design layout from a design stage, determining one or more design constructs based on an analysis of the data stream, determining one or more instructions to implement the one or more design constructs at the design stage, and sending the instructions to the design stage to implement the one or more design constructs.