IC Layout White Space Reuse for Power Grid Reinforcement
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Solution Overview
Problem
Existing methods for designing semiconductor integrated circuits face challenges in efficiently utilizing white spaces and optimizing power and ground wirings, leading to suboptimal performance and integration efficiency.
Innovation Solution
A method and system for designing semiconductor integrated circuits that involve determining a first layout through placement and routing, identifying a target region for additional power and ground wirings, and modifying the layout to include these wirings, utilizing white spaces effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a placement and routing procedure is performed to determine the layout of the semiconductor integrated circuit, then the circuit components can be placed and connected, but white spaces are not efficiently utilized and power and ground wiring distribution is suboptimal
Solution Approach 1:
The method performs preliminary identification of target regions capable of accommodating additional power and ground wirings before finalizing the layout. By selecting target regions in advance and planning additional wiring placements, the method optimizes power and ground distribution before completing the overall layout design, thereby improving both robustness and integration efficiency
Solution Approach 2:
The method identifies specific target regions within the layout where additional power and ground wirings can be effectively placed. By focusing on local regions rather than uniformly distributing wirings throughout the entire circuit, the method optimizes power and ground delivery to specific areas that need them most, improving both reliability and space utilization
2Reliability
If additional power and ground wirings are added to optimize distribution, then robustness improves, but layout complexity increases
Solution Approach 1:
Instead of uniformly adding power and ground wirings throughout the entire layout, the method identifies and targets specific regions where additional wirings are most needed. This localized approach improves power and ground distribution robustness while minimizing the overall increase in layout complexity by concentrating modifications only where necessary
Solution Approach 2:
The method adds only the necessary number of additional power and ground wirings in target regions rather than comprehensively adding wirings throughout the entire circuit. This partial action approach provides sufficient improvement in distribution robustness without unnecessarily increasing layout complexity
3Productivity
If white spaces are utilized for additional wirings, then integration efficiency improves, but routing difficulty increases
Solution Approach 1:
The method performs preliminary identification of target regions that can accommodate additional power and ground wirings before finalizing the routing. By planning the placement of additional wirings in advance in identified target regions, the method simplifies the routing process rather than making ad-hoc decisions during detailed routing, thereby improving integration efficiency without excessively increasing routing difficulty
Data Source
AI summary
A method of designing a layout of a semiconductor integrated circuit, including receiving input data defining the semiconductor integrated circuit; determining a first layout of the semiconductor integrated circuit by performing a placement and routing (P&R) procedure based on the input data, wherein the first layout includes a plurality of blocks, a plurality of standard cells, a plurality of power wirings, a plurality of ground wirings, a plurality of clock wirings, and a plurality of signal wirings; selecting a target region of the first layout, wherein the target region is capable of accommodating at least one additional power wiring and at least one additional ground wiring; and determining a second layout of the semiconductor integrated circuit by modifying the first layout to include the at least one additional power wiring and the at least one additional ground wiring in the target region.