IC Layout Design Methodology with Process Variation Bands
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Solution Overview
Problem
Current integrated circuit design processes lack a reliable method to account for and compensate for variations in photolithographic process conditions, leading to potential manufacturing issues and reduced yield due to sensitivity to focus, dose, and other process variations.
Innovation Solution
The method involves calculating process variation bands (PV-bands) to determine the range of object dimensions that can be printed under various process conditions, allowing for the ranking of IC layouts by manufacturability and identifying necessary design adjustments to ensure robustness across different manufacturing scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional verification checks are performed without considering process variations, then the design verification process is simple and fast, but the circuit may fail to operate correctly under varying manufacturing conditions
Solution Approach 1:
The patent applies preliminary action by calculating process variation bands (PV-bands) during the design verification stage, before actual manufacturing occurs. The PV-bands pre-characterize the range of dimensional variations objects may exhibit under different process conditions, allowing designers to proactively identify and correct potential manufacturing issues in the layout before fabrication, thus ensuring reliability without adding complexity to the manufacturing process itself.
Solution Approach 2:
The patent introduces a new dimensional aspect to layout verification by adding PV-bands as an additional layer of geometric information around existing layout objects. This dimensional extension allows the verification process to account for process variations in a systematic way, transforming a two-dimensional layout check into a three-dimensional analysis that includes the variation envelope, thereby improving reliability while maintaining manageable complexity through automated computation.
2Manufacturing precision
If PV-bands are calculated and analyzed to account for process variations, then manufacturability and yield are improved, but the verification process becomes more complex and computationally intensive
Solution Approach 1:
The patent replaces complex manual or rule-based verification methods with an automated computational system that calculates PV-bands using process characterization data. Instead of relying on designer expertise or simple geometric rules, the system automatically computes the variation bands by simulating process effects on the layout, substituting mechanical/manual verification processes with algorithmic computation that handles the complexity while providing precise manufacturability assessment.
Solution Approach 2:
The PV-band calculation acts as an intermediary between the layout design and the manufacturing process. Rather than directly analyzing complex process variations against the layout, the patent introduces PV-bands as an intermediate geometric representation that captures the essence of process variation effects. This intermediary layer simplifies the verification process by providing a clear, visual, and computable metric for assessing manufacturability under variations.
3Adaptability or versatility
If traditional design rule checks are used without process variation consideration, then the verification process is straightforward, but the circuit layout may not be robust against focus, dose, and other photolithographic variations
Solution Approach 1:
The patent applies local quality by calculating PV-bands for individual layout objects or critical regions rather than applying uniform verification rules across the entire design. This allows different parts of the layout to be assessed with appropriate levels of detail and variation characterization, focusing computational resources on critical areas while maintaining ease of manufacture for non-critical regions, thus balancing robustness with verification simplicity.
Data Source
AI summary
A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.