Integrated Circuit Layout Optimization via Quality Number Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for optimizing integrated circuit layouts do not effectively utilize quality number assessments to propose modified designs that improve manufacturing yield, as they primarily focus on pass/fail criteria without incorporating quality number feedback for design optimization.
Innovation Solution
A method that assesses local quality numbers in integrated circuit layouts, aggregates these to derive an integral quality number, and perturbs the layout to optimize the quality number, allowing for the selection of perturbations that enhance the design's manufacturing yield by varying the global circuit layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single quality number statements are provided for pass/fail assessment, then manufacturing yield can be evaluated, but the information is not used to propose modified designs
Solution Approach 1:
The patent implements feedback by using the quality number assessment results to guide layout modifications. The system calculates quality numbers for different layout configurations and uses this information to iteratively improve the design, transforming static pass/fail evaluation into dynamic optimization guidance
Solution Approach 2:
The system performs self-service by automatically generating modified design proposals based on quality number assessments without requiring manual intervention. The optimization process autonomously identifies problematic areas and suggests corrective layout changes
2Manufacturing precision
If design rule checking is performed with minimal distance requirements, then manufacturing compliance is ensured, but manufacturing yield can be improved by preferring more than minimal distance
Solution Approach 1:
The patent applies parameter changes by transitioning from fixed minimal distance design rules to variable spacing optimized by quality number assessment. The system adjusts inter-element distances beyond minimal requirements based on calculated quality metrics, achieving both compliance and yield improvement
Solution Approach 2:
The system performs preliminary action by calculating quality numbers and assessing manufacturing risks before final production. This advance evaluation allows optimization of spacing parameters to prevent yield issues before manufacturing begins
Data Source
AI summary
The invention relates to a method of optimizing an integrated circuit layout, wherein an initial integrated circuit layout is provided. A predetermined set of physical characteristics of a predetermined set of polygons of said initial circuit layout, is assessed and said physical characteristics are aggregated to derive an integral quality number associated to said initial circuit layout. According to the invention, cost functions are generated to evaluate a perturbed quality number of said perturbed layout and layout perturbations are selected that optimize the quality number, so that the circuit layout is optimized.