IC Layout Partial Re-routing for Bridging Prevention
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Solution Overview
Problem
Current IC device manufacturing processes face challenges such as optical proximity effects, mask pattern fidelity issues, and photoresist processing limitations, leading to errors in patterning, reduced throughput, higher costs, and lower yields, particularly due to complex designs and miniaturization efforts.
Innovation Solution
A method for identifying and partially re-routing selected areas in IC designs, including critical areas, by comparing design data against manufacturing criteria, and performing partial re-routing to meet these criteria through techniques like forming staircase-like extensions or widening metal segments, thereby improving manufacturing process margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical proximity correction (OPC) models are utilized to optimize photomask for substrate processing, then resolution and pattern transfer reliability are improved, but manufacturing complexity and processing time increase
Solution Approach 1:
The patent performs preliminary identification of critical layout areas and pre-modifies the design data before actual manufacturing. By detecting potential bridging issues and spacing problems in advance, and applying staircase extensions or via shifts beforehand, the manufacturing process becomes simpler and more reliable without requiring complex real-time OPC adjustments.
Solution Approach 2:
The patent segments the manufacturing optimization into specific critical areas rather than applying complex OPC to the entire design. By identifying and treating only those layout regions with potential bridging or spacing issues, the solution reduces overall manufacturing complexity while maintaining pattern transfer reliability in critical regions.
2Area of moving object
If design miniaturization is pursued to increase integration density, then device functionality is improved, but manufacturing process margins are reduced and errors increase
Solution Approach 1:
The patent applies local quality enhancement by adding staircase extensions specifically to metal segments in critical areas and adjusting via positions where needed, rather than uniformly scaling the entire design. This localized modification maintains the miniaturized integration density while improving manufacturing precision in specific problem areas through geometric adjustments that increase spacing and reduce bridging risks.
3Reliability
If spacing between connecting vias is increased to prevent bridging, then manufacturing reliability is improved, but layout area and device size increase
Solution Approach 1:
The patent resolves the spacing conflict by transitioning to another dimension - adding staircase extensions that create vertical/staggered spacing between metal segments connected to adjacent vias. This dimensional approach increases the effective spacing between conductive elements to prevent bridging without requiring horizontal separation that would increase layout area, thereby maintaining compact device footprint while improving manufacturing reliability.
Data Source
AI summary
Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.