Integrated Circuit Layout Editing Using Reference Frames
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Solution Overview
Problem
The complexity of designing and modifying the layout of very-large-scale integrated circuits, especially after routing of interconnections has been performed, is time-consuming and error-prone, requiring significant manual effort and often necessitates costly re-routing due to late-stage floorplan changes.
Innovation Solution
A method and system that utilize horizontal and vertical reference frames to efficiently move subchip components and top-level wiring, allowing for accurate and efficient modification of the floorplan layout after routing, reducing errors and manual re-routing efforts by using a computer system to redefine and update the positions of subchips and wire segments within these frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional manual methods are used to modify floorplan layout after routing, then design flexibility is maintained, but time consumption and error rate increase significantly
Solution Approach 1:
The patent introduces reference frames as intermediary objects that mediate between the floorplan modification request and the actual layout elements. When a reference frame is moved, it automatically updates the positions of all contained subchips and wire segments through offset calculations, serving as a mediator that translates a single user action into coordinated updates of multiple layout elements without requiring manual intervention for each element
Solution Approach 2:
The patent uses offset values to create a relative positioning model where the positions of subchips and wire segments are stored as offsets from reference frame boundaries rather than absolute coordinates. This copying approach allows the entire group of elements within a reference frame to be relocated by simply changing the reference frame's position, automatically replicating the relative positioning relationships without manual re-positioning of each element
2Ease of operation
If conventional manual methods are used to modify floorplan layout after routing, then design control is maintained, but error rate increases
Solution Approach 1:
Reference frames act as intermediaries that automatically manage the coordination between multiple layout elements. When a reference frame is moved, the system automatically calculates and updates the new positions of all contained elements using stored offset values, eliminating manual coordination errors that would occur when designers try to update multiple elements individually
Solution Approach 2:
The system maintains offset values that represent the relative positioning relationships between reference frames and contained elements. This feedback mechanism ensures that when reference frames are moved, the offset information is used to automatically update element positions, providing continuous verification and correction of positioning relationships to prevent errors
3Productivity
If late-stage floorplan changes are made using conventional methods, then design optimization is achieved, but costly re-routing is required
Solution Approach 1:
The patent stores wire segment positions as offsets from reference frame boundaries rather than absolute coordinates. When reference frames are moved during late-stage design optimization, the offset copying mechanism automatically updates wire segment positions without requiring actual re-routing of connections, thereby achieving design optimization without incurring re-routing costs
Solution Approach 2:
The patent extracts the relative positioning information (offsets) from the absolute position data of layout elements. By separating the reference frame position from the element positions and storing only the relative offsets, the system enables independent movement of reference frames without affecting the actual interconnections, thereby extracting the positioning flexibility needed for late-stage optimization without triggering costly re-routing
Data Source
AI summary
An automated system, and method of operating the same, for editing the floorplan, placement, and toplevel wiring routing in a layout of an integrated circuit. Components in the layout of the integrated circuit, such components including functional blocks or subchips, and also wire segments of the toplevel wiring, are associated with horizontal reference frames and vertical reference frames. Each reference frame has its position, in the orthogonal direction, specified by a position of a reference line. The positions of subchips and wire segments within the reference frame are expressed as offsets from the reference line. Movement of components is accomplished by moving the reference frame in the orthogonal direction, and updating the reference line position while maintaining the offset values constant.