Region-Based IC Layout Shrinking for DRC-Compliant Migration
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Solution Overview
Problem
The linear shrink approach in IC design layout migration leads to manual adjustments that introduce errors, particularly in non-shrinkable circuits, and results in a high number of design rule check (DRC) errors during the transition to a newer fabrication process.
Innovation Solution
A non-uniform shrinking method is applied, where different scaling factors are used for shrinkable and non-shrinkable regions in the IC design layout, maintaining the size of non-shrinkable features while adjusting shrinkable features, thereby reducing errors and improving design rule compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a linear shrink approach is used for IC design layout migration, then the layout can be uniformly scaled to a newer fabrication process, but manual adjustments are required that introduce errors and result in a high number of design rule check errors
Solution Approach 1:
The layout is divided into multiple regions with different shrinkage characteristics. Each region is assigned a specific shrinkage factor based on its circuit type and design requirements, allowing differential scaling that maintains design rule compliance while improving migration efficiency
Solution Approach 2:
Different regions of the layout are assigned different quality attributes regarding shrinkage. Some regions are marked as shrinkable while others are protected, enabling localized scaling decisions that preserve critical design rules in specific areas while allowing optimization in others
2Device complexity
If uniform shrinking is applied to all regions, then the layout migration process is simplified, but non-shrinkable circuits require manual adjustments that introduce errors
Solution Approach 1:
The shrinkage factor is made dynamic and region-dependent rather than uniform. The system automatically determines appropriate shrinkage factors for different regions based on pre-defined rules and circuit characteristics, eliminating the need for manual adjustments while maintaining high accuracy
Solution Approach 2:
The layout migration system performs self-adjustment by automatically identifying shrinkable and non-shrinkable regions and applying appropriate scaling factors without requiring manual intervention. This automated self-service approach eliminates human errors while maintaining layout accuracy
Data Source
AI summary
A method of making a semiconductor device includes receiving a first layout of a device. The first layout includes a first plurality of conductive patterns spaced along a first direction, wherein the first plurality of conductive patterns is in a first region, a second plurality of conductive patterns spaced along the first direction, wherein the second plurality of conductive patterns is in a second region, and a first interconnect pattern for electrically connecting at least one of the first plurality of conductive patterns to at least one of the second plurality of conductive patterns, wherein the first interconnect pattern is on a different layer from the first plurality of conductive patterns. The method includes scaling the first plurality of conductive patterns using a first scaling factor. The method further includes scaling the second plurality of conductive patterns using a second scaling factor different from the first scaling factor.