IC Layout Electrical Property Simulation with RET Correction
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Solution Overview
Problem
Conventional methods for estimating electrical properties of integrated circuit features are inaccurate when significant photolithographic and process distortions occur, causing features created on a wafer to deviate significantly from the desired layout pattern.
Innovation Solution
The method involves using resolution enhancement techniques (RETs) such as optical and process correction (OPC) to correct the integrated circuit layout design, followed by print image simulation to generate a simulated layout image that accurately reflects the features as they will be formed on the wafer, which is then input into a field solver program to estimate electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional field solver programs are used to estimate electrical properties, then the computation is simple and fast, but the accuracy deteriorates when significant photolithographic distortions occur
Solution Approach 1:
The patent applies resolution enhancement techniques (RETs) such as optical and process correction (OPC) to the layout design before performing electrical property estimation. This preliminary correction of the layout pattern accounts for anticipated photolithographic distortions, allowing the field solver to compute electrical properties based on a pre-corrected geometry that better predicts actual manufactured features, thereby improving accuracy without requiring a fundamentally different computation approach
2Measurement precision
If resolution enhancement techniques (RETs) are applied to correct the layout design, then the accuracy of electrical property estimation improves, but the computation time and processing complexity increase
Solution Approach 1:
The layout design is corrected using RETs before the field solver computation, preparing the geometry in advance to account for photolithographic distortions. This preliminary correction step, while adding processing time, avoids the need for iterative recalculations and enables a single-pass field solver computation that achieves higher accuracy
Solution Approach 2:
The patent introduces a print image simulation as an intermediary step between the corrected layout design and the field solver computation. This simulation generates a simulated layout image that represents the anticipated manufactured features, serving as a bridge that translates the corrected design into a format optimized for electrical property computation, thereby improving the efficiency and accuracy of the overall process
Data Source
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AI summary
A system for calculating electrical properties of features to be created in an integrated circuit. All or a portion of a desired layout design is corrected for photolithographic or other process distortions using one or more resolution enhancement techniques. A simulated layout image of a corrected layout is used as an input to a field solver program that calculates the electrical properties of the features as they will be printed on a wafer.