Local IC Layout Rearrangement to Avoid Reticle Defects
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor integrated circuits (ICs) lead to challenges in avoiding defects on photomasks, which can cause device failures and low yields, as existing methods of forming patterned reticles are inadequate in addressing these issues, especially when critical features land on defects.
Innovation Solution
A local re-arrangement of IC layouts is performed by swapping or detouring functionally equivalent blocks and modifying interconnect elements to bypass defects on the reticle, ensuring critical features do not intersect with defects, while maintaining design rule compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods of forming patterned reticles are used, then manufacturing process is simple, but reticle defects cause device failures and low yields
Solution Approach 1:
The patent applies preliminary action by detecting reticle defects before pattern transfer and pre-rearranging the IC layout to avoid defects. The system identifies defect locations in advance, determines which critical features would be affected, and repositions layout blocks before manufacturing, preventing device failures proactively rather than reacting to defects after pattern transfer.
Solution Approach 2:
The patent applies local quality by performing targeted layout re-arrangement only in regions affected by reticle defects rather than globally modifying the entire layout. The system identifies specific layout blocks that would intersect with defects and repositions only those blocks, maintaining manufacturing simplicity in unaffected areas while improving yield in defect-prone regions.
2Productivity
If geometry sizes are shrunk and pattern density is increased, then functional density is improved, but it becomes increasingly difficult to avoid reticle defects
Solution Approach 1:
The patent applies feedback by using defect detection information to dynamically adjust the IC layout. The system detects reticle defects, feeds this information back to the layout design stage, and automatically repositions affected layout blocks. This closed-loop approach enables high pattern density to be maintained while adapting the layout in real-time to avoid defects, ensuring both productivity and reliability.
3Reliability
If critical features are repositioned to avoid defects, then device reliability is improved, but layout design complexity increases
Solution Approach 1:
The patent applies self-service by implementing automated layout re-arrangement algorithms that perform the repositioning operation without manual intervention. The system automatically identifies critical features affected by defects, calculates optimal repositioning strategies, and generates modified layout data. This automation maintains ease of manufacture by eliminating the need for manual layout redesign while ensuring device reliability through precise defect avoidance.
Data Source
AI summary
Provided is a method of fabricating a semiconductor device. An integrated circuit (IC) layout plan is obtained. The IC layout plan contains critical features and non-critical features. Locational information regarding a defect on a blank reticle is obtained. The blank reticle is a candidate reticle for being patterned with the IC layout plan. Based on the locational information regarding the defect and the IC layout plan, a determination is made that at some of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan, regardless of whether the IC layout plan is globally manipulated or not before being patterned onto the blank reticle. In response to the determination, selected local portions of the IC layout plan are re-arranged such that none of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan.