Parameterized Layout Component Reuse in IC Design
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Solution Overview
Problem
Existing IC design methods face challenges in achieving uniform layout and synchronization of layout clones across different designs, leading to non-uniform transistor implementations that can impact electrical characteristics, and lack re-usability of design cell layouts across designs.
Innovation Solution
The use of a schematic driven layout generation tool that applies parameter values from a higher-level schematic design to create core layout cells, which are re-usable across different designs, ensuring uniformity and synchronization of layout clones through a pedigree-based system, allowing for automatic generation of geometric structures and instances of layout cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a schematic design is converted to layout design using existing methods, then layout generation is achieved, but uniformity and synchronization of layout clones across different designs cannot be maintained
Solution Approach 1:
The patent creates a universal layout generation system where schematic design cells with hierarchical parameters serve as templates that can be applied across multiple different IC designs. The layout generation tool accepts schematic cells as input and produces consistent layout clones that can be reused in different design contexts, achieving both uniformity and versatility.
Solution Approach 2:
The patent uses hierarchical parameters that can be instantiated at different levels of the design hierarchy. By passing parameter values from parent cells to child cells through the schematic design layer, the system maintains parameter consistency across different designs while allowing for necessary variations, ensuring uniform layout generation with adaptability.
2Reliability
If layout clones are generated without a pedigree-based system, then generation speed is maintained, but synchronization and consistency of layout clones across designs cannot be ensured
Solution Approach 1:
The patent implements a copying mechanism where layout clones are created as copies of master layout cells with preserved pedigree information. The pedigree acts as a metadata layer that tracks the hierarchy and parameter relationships, enabling automatic synchronization without requiring complex manual management systems.
Solution Approach 2:
The patent establishes a feedback mechanism where changes to master layout cells automatically propagate to all descendant layout clones through the pedigree-based hierarchy. This feedback loop ensures synchronization across designs while the automated nature of the process keeps the management complexity manageable.
3Productivity
If manual methods are used for layout generation, then control over geometric structures is maintained, but productivity and efficiency of IC design process are reduced
Solution Approach 1:
The patent implements a self-service layout generation system where the schematic design cells automatically generate their corresponding layout representations through the layout generation tool. The hierarchical parameter system automatically propagates values through the design hierarchy, eliminating the need for manual intervention while maintaining design control and improving productivity.
Solution Approach 2:
The patent replaces manual mechanical layout creation processes with an automated computational system. The layout generation tool uses algorithmic processing of schematic design cells and hierarchical parameters to automatically produce layout results, substituting manual operations with automated mechanics that improve both productivity and ease of operation.
Data Source
AI summary
A method is provided to produce an integrated circuit layout design comprising: providing in non-transitory storage a pPar parent cell that includes one or more pPar instances and that specifies one or more corresponding input parameter values; producing a graphical representation on a computer display screen of a first schematic design that includes a pPar parent instance; instantiating in non-transitory storage a parameterized cell supermaster that corresponds to the pPar parent cell; determining whether a core layout cell is stored in non-transitory storage that corresponds to the parameterized cell supermaster and the one or more corresponding input parameter values; in response to determining that such a core layout cell is stored, filling a first parameterized cell submaster with an instance of the stored core layout cell; in response to determining that such a core layout cell is not stored, using program code associated with the parameterized cell supermaster to generate a core layout cell; and storing the generated core layout cell in non-transitory storage.