Multi-patterning IC Layout Conflict Resolution via Safe Independent Nodes
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Solution Overview
Problem
In semiconductor fabrication, multi-patterning technologies face challenges in designing layouts that comply with minimum separation distances, leading to conflicts and restrictions on layout choices, especially at smaller technology nodes like 45 nanometers, where photoresist patterns begin to blur, and existing methods like double or triple patterning struggle to efficiently assign circuit patterns to photomasks without increasing the number of masks or introducing unnecessary restrictions.
Innovation Solution
The method involves identifying and modifying layouts to ensure every sub-G0 odd loop has at least one safe independent node, allowing for systematic assignment of circuit patterns to multiple photomasks using an electronic design automation tool, which systematically identifies and modifies the layout to eliminate conflicts by selecting safe independent nodes and assigning patterns to photomasks, ensuring compliance with multi-patterning technology standards without increasing the number of masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-patterning technology is used to pattern smaller features at 45nm node, then manufacturing precision is improved, but layout complexity increases due to MPT conflicts and separation distance constraints
Solution Approach 1:
The patent segments the layout into multiple color groups (M-coloring) where each color represents a separate photomask assignment. By dividing the circuit patterns into M distinct color groups and assigning each group to a different photomask, the method resolves MPT conflicts by ensuring minimum separation distances are maintained within each color group, thereby enabling manufacturing of sub-45nm features while managing layout complexity through systematic segmentation
Solution Approach 2:
The patent introduces a new dimension of mask assignment by extending traditional two-color double patterning to M-color multi-patterning. This dimensional extension allows patterns to be assigned to multiple photomasks (M dimensions) rather than just two, providing additional degrees of freedom to resolve conflicts and maintain separation distances, thus improving manufacturing precision without excessive layout complexity
2Manufacturing precision
If minimum separation distances are enforced for each mask to avoid MPT conflicts, then manufacturing precision is improved, but design flexibility is reduced
Solution Approach 1:
The patent changes the parameter of separation distance enforcement from a global constraint to a localized constraint specific to each color group. By assigning different separation distance requirements to different color groups and their corresponding photomasks, the method maintains manufacturing precision while allowing greater layout flexibility, as designers can optimize each color group independently rather than adhering to uniform separation constraints across the entire layout
3Manufacturing precision
If the number of photomasks is increased to resolve MPT conflicts, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies partial action by using exactly M photomasks where M is the minimum number needed to resolve all MPT conflicts in the layout. Rather than increasing the number of photomasks beyond what is necessary, the method calculates the optimal M-coloring solution that resolves conflicts with the minimal required number of masks, thereby maintaining manufacturing precision while avoiding unnecessary increases in device complexity and fabrication cost
Data Source
AI summary
A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.