Selective IC Layout Scaling with Variable Line Widths
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Solution Overview
Problem
Current methods for scaling down integrated circuit layouts universally shrink all dimensions, including the gate conductor layer, which can alter the electronic characteristics of devices and render them non-functional, necessitating costly and time-consuming redesigns.
Innovation Solution
A novel circuit layout structure and method that differentiates line widths and pitches between regions, allowing for selective scaling down while maintaining original electronic characteristics by applying distinct scaling rules to conductive lines in different regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If universal scaling down is applied to all dimensions of the IC layout, then the IC size is reduced, but the electronic characteristics of devices are compromised
Solution Approach 1:
The IC layout is divided into multiple regions, with the first region subjected to scaling down and the second region maintained at original dimensions. This segmentation allows selective application of scaling to different portions of the circuit, enabling size reduction in non-critical areas while preserving device performance in critical regions.
Solution Approach 2:
Different scaling rules are applied to different regions of the IC layout. The first region uses a first scaling rule that reduces dimensions, while the second region uses a second scaling rule that maintains original characteristics. This local differentiation ensures that only areas where size reduction is acceptable undergo scaling, while sensitive device regions retain their electronic characteristics.
2Reliability
If IC layout is redesigned to maintain device characteristics after scaling, then electronic characteristics are preserved, but design cost and time increase
Solution Approach 1:
The IC layout is pre-divided into regions with different scaling requirements before the scaling process. By identifying and marking the first and second regions in advance, the subsequent scaling operation can be automatically applied without requiring time-consuming post-scaling redesign or manual adjustment of individual components.
Solution Approach 2:
The patent applies different scaling parameters (first scaling rule vs. second scaling rule) to different regions. This parameter differentiation allows the scaling process to automatically preserve electronic characteristics in the second region while reducing size in the first region, eliminating the need for iterative redesign and manual optimization.
3Quantity of substance
If gate conductor layer size is reduced through scaling, then IC density increases, but device performance deviates excessively
Solution Approach 1:
The layout is segmented into regions where the gate conductor layer is treated differently. In the second region, the gate conductor layer maintains its original size to preserve device performance, while in the first region, spacing and other non-gate elements are scaled to increase overall density without compromising the critical gate dimensions.
Solution Approach 2:
The scaling operation applies local quality differentiation by maintaining original gate conductor dimensions in the second region while allowing size reduction in other areas of the first region. This ensures that device performance is preserved where gates are present, while density increases in regions where gate scaling would not critically impact performance.
Data Source
AI summary
A method scales down an integrated circuit layout structure without substantially jeopardizing electronic characteristics of devices. First, a conductive line set includes a first conductive line and a second conductive line respectively passing through a first region and a second region. Second, a sizing-down operation is performed so that the first conductive line and the second conductive line respectively have a first region scaled-down line width, a first region scaled-down space and a first region scaled-down pitch in the first region as well as selectively have a second region original line width, a second region scaled-down space and a second region scaled-down pitch in the second region. The first region scaled-down line width and the second region original line width are substantially different from each other.