IC Layout Validation Using SEM Images and Machine Learning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional IC layout validation methods face challenges in accurately identifying design violations due to multiple translations of design requirements into design rule check (DRC) code, leading to potential loss of design information and inefficiencies.
Innovation Solution
Employing a trained machine learning model, such as a neural network, to analyze IC layout patterns using supervised learning with SEM images, identifying good and bad designs, and generating a prediction model for IC layout validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional DRC code translation methods are used to validate IC layouts, then the validation process can be automated, but design information is lost during multiple translations and accuracy decreases
Solution Approach 1:
The patent extracts the essential layout pattern information directly from SEM images, bypassing the traditional DRC code translation process. By taking out the critical geometric and topological features directly from manufacturing data, the system avoids multiple translation steps that cause information loss, thereby improving validation accuracy while preserving design information.
2Productivity
If traditional DRC code translation methods are used, then existing validation tools can be utilized, but the process becomes inefficient and time-consuming
Solution Approach 1:
The patent replaces the mechanical translation process (converting design requirements through multiple intermediate DRC code representations) with a direct machine learning-based analysis system. This substitution eliminates the time-consuming translation steps while utilizing existing SEM image data, significantly improving validation efficiency and reducing processing time.
3Measurement precision
If machine learning models are used for IC layout validation, then validation accuracy and speed improve, but the complexity of implementing and training the model increases
Solution Approach 1:
The patent implements a self-service approach where the machine learning model is trained using actual SEM images from the specific manufacturing process. The model learns directly from the data it will analyze, automatically adapting to process-specific variations without requiring complex manual configuration or extensive external training datasets, thereby reducing implementation complexity while maintaining high accuracy.
Data Source
AI summary
Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.