Integrated Circuit Layout Design with Shortest Path Routing
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Solution Overview
Problem
As semiconductor technology advances, the design of integrated circuits becomes increasingly complex, leading to issues such as design rule violations and timing violations due to the complexity of wiring paths, which can result in electrical performance quality variations and design quality deterioration.
Innovation Solution
A method for designing integrated circuit layouts that involves generating floorplan data, distinguishing routable and non-routable regions, and performing a shortest path search operation to optimize wiring paths, thereby reducing verification and correction time and improving design quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration increases to advance semiconductor technology, then the circuit functionality and element count improve, but the wiring complexity increases leading to design rule violations and timing violations
Solution Approach 1:
The patent performs a preliminary shortest path search between specified points (cells and ports) before finalizing the layout. By calculating and verifying wiring paths in advance using floorplan data, the system identifies potential timing violations and routing issues early in the design process, allowing corrections to be made before manufacturing, thus resolving the wiring complexity issues that arise from high integration
2Manufacturing precision
If wiring paths are not optimized, then the layout design process is simpler, but timing delay increases and design quality deteriorates
Solution Approach 1:
The system performs preliminary shortest path searches and timing verification using floorplan data before final layout completion. This early verification identifies timing violations and suboptimal wiring paths, allowing designers to adjust the layout proactively. Although this adds an initial verification step, it prevents extensive rework later and reduces overall design iteration time, thereby improving design quality while managing verification time efficiently
Solution Approach 2:
The patent implements a feedback mechanism where the results of shortest path searches and timing analysis are used to guide layout adjustments. The system continuously verifies wiring paths and provides feedback on timing violations, enabling iterative optimization of the layout to achieve both short wiring paths and high design quality
3Productivity
If manual verification of wiring paths is performed, then design flexibility is maintained, but time and resources required for verification and correction increase
Solution Approach 1:
The system performs automated shortest path searches and timing verification using algorithms that automatically analyze floorplan data and calculate wiring paths between specified points. This self-service approach eliminates the need for manual verification, allowing the system to independently identify timing violations and routing issues, thereby significantly improving verification efficiency and reducing both verification and correction time
Solution Approach 2:
The patent replaces manual verification processes with automated computational algorithms. Instead of relying on manual inspection and adjustment of wiring paths, the system uses computer-based shortest path search algorithms to automatically analyze and verify timing constraints, substituting mechanical human effort with automated electronic computation to enhance productivity and reduce correction time
Data Source
AI summary
A method of designing a layout of an integrated circuit includes generating floorplan data by performing floorplan based on input data for the integrated circuit, searching for a path between a first point and a second point, which are specified, the searching based on the floorplan data, and positioning components of the layout based on a result of the searching. The searching for the path includes distinguishing based on the floorplan data a first region where routing is possible from a second region where the routing is not possible, receiving position data on the first point and the second point, and searching for a shortest path between the first point and the second point, on the first region.