IC Layout Weak-Point Detection for EUV Stochastic Defects
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Solution Overview
Problem
Conventional semiconductor fabrication processes face limitations in densely etching circuit patterns due to defects such as pattern bridges, and the increased influence of quantum fluctuations in extreme ultraviolet light sources leads to stochastic pattern defects, which are difficult to predict and prevent.
Innovation Solution
A method that models quantum mechanical variability of light intensity on a photoresist to calculate line edge roughness and a variability constant, allowing for the prediction of stochastic weak points in semiconductor integrated circuit layout patterns by simulating the polymer concentration and intensity distribution, thereby identifying potential defects before fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic processes are used to form circuit patterns, then fabrication can be performed with existing technology, but defects such as pattern bridges occur and manufacturing precision deteriorates
Solution Approach 1:
The invention performs preliminary detection of stochastic weak points in the layout pattern before the actual photolithography fabrication process. By calculating line edge roughness and identifying vulnerable regions in advance, the system enables preliminary design modifications to avoid these weak points, preventing defects before they occur during manufacturing.
Solution Approach 2:
The invention replaces physical trial-and-error fabrication with a computational modeling system. It uses optical simulation and statistical analysis to predict pattern formation outcomes, substituting mechanical/chemical fabrication iterations with information-based prediction and optimization.
2Manufacturing precision
If extreme ultraviolet light sources are used to achieve finer patterns, then manufacturing precision improves, but quantum fluctuations increase causing stochastic pattern defects
Solution Approach 1:
The invention introduces feedback by using the results of optical simulation and line edge roughness calculation to guide layout pattern optimization. The system provides feedback information about stochastic weak points, allowing designers to modify patterns to avoid these regions and reduce defect rates.
Solution Approach 2:
The invention changes the approach from directly controlling fabrication parameters to controlling design parameters. By modifying layout pattern geometry and configuration based on simulated weak point analysis, the system optimizes pattern formation while accounting for quantum fluctuations in EUV lithography.
3Manufacturing precision
If layout patterns are designed without stochastic weak point analysis, then design complexity is reduced, but manufacturing precision deteriorates due to undetected defect-prone regions
Solution Approach 1:
The invention enables the layout pattern design process to self-optimize by automatically detecting stochastic weak points through computational modeling. The system performs self-analysis of the layout, identifies vulnerable regions, and provides guidance for improvement without requiring external experimental validation.
Solution Approach 2:
The invention performs preliminary optimization of the layout pattern by identifying and addressing stochastic weak points before fabrication. This advance analysis prevents defects from occurring in the first place, eliminating the need for costly post-fabrication corrections or rework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the prediction of stochastic defects in the patterning process, allowing for the prevention of patterning defects by designing around identified weak points and setting process limits, thus improving the precision and reliability of semiconductor device fabrication.
Implementation Method 1
exposing a wafer, masked by a layout pattern and coated with a photoresist, to light from a light source
Implementation Method 2
etching the semiconductor integrated circuit according to the layout pattern
Data Source
AI summary
A method for detecting a stochastic weak point of a layout pattern of a semiconductor integrated circuit includes: forming a semiconductor integrated circuit by exposing a wafer which is masked by a layout pattern and coated with a photoresist to light, and etching the circuit according to the layout pattern, calculating line edge roughness (LER) of the circuit, and calculating a variability constant for fitting the line edge roughness to a normal distribution from a polymer concentration value of the photoresist. The polymer concentration value is calculated from modeling the layout pattern, a total value of intensity of light reaching the photoresist, and an intensity value of light reaching one point of the photoresist. The method further includes calculating a probability distribution of the polymer concentration value of the layout pattern based on the variability constant, and calculating a stochastic weak point of the layout pattern from the probability distribution.