IC Transistor Layout Using Short Gates and Strain Structures
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Solution Overview
Problem
The performance of integrated circuit (IC) devices is limited by local layout effects, such as strain caused by the proximity of semiconductor devices to other features, which can lead to variations in electrical characteristics and reduced performance, especially as transistor scaling introduces stronger interactions and material strain.
Innovation Solution
The IC device layout is optimized by using shorter gates, dummy gates, and fin trim isolation structures to create local layout effects that enhance performance, including arranging transistors in columns or rows with shared support structures and incorporating dielectric structures to trigger three-dimensional strain effects, thereby increasing operating current and improving performance beyond current devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor scaling is continued to increase device density, then device integration is improved, but local layout effects such as strain cause variations in electrical characteristics and reduce performance
Solution Approach 1:
The patent applies local quality by introducing dummy gates and fin trim isolation structures at specific locations around active transistors. These structures create localized strain fields in the channel region of transistors, enhancing carrier mobility and electrical performance. The dummy gates are positioned adjacent to active gates, and fin trim isolation structures are placed between fins, creating targeted local effects without altering the overall transistor scaling architecture.
2Power
If dummy gates and fin trim isolation structures are added to enhance strain effects, then operating current is improved, but device complexity increases
Solution Approach 1:
The dummy gates serve multiple functions: they create strain effects to enhance carrier mobility, act as placeholders for future transistor locations, and provide mechanical support structures. The fin trim isolation structures similarly serve dual purposes by creating localized strain while also isolating adjacent fins electrically and mechanically. This multi-functionality reduces the need for additional separate structures.
Solution Approach 2:
The patent merges the functions of strain induction and structural support into single elements. The dummy gates combine strain generation with structural framework provision, while fin trim isolation structures combine electrical isolation with strain enhancement. This merging reduces overall device complexity compared to having separate dedicated structures for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized layout results in IC devices with operating currents up to 15% higher than existing devices, offering better performance through strategic placement of gates and dielectric structures that enhance strain on transistors.
Implementation Method 1
incorporating dielectric structures to trigger three-dimensional strain effects, thereby increasing operating current
Data Source
AI summary
An IC device may include an array of transistors. The transistors may have separate gate electrodes. A gate electrode may include polysilicon. The gate electrodes may be separated from each other by one or more electrical insulators. The separated gate electrodes have shorter lengths, compared with connected gate electrodes, which can optimize the performance of the IC device due to local layout effect. Also, the IC device may include conductive structures crossing the support structures of multiple transistors. Such conductive structures may cause strain in the IC device, which can boost the local layout effect. The conductive structures may be insulated from a power plane. Alternatively or additionally, the IC device may include dielectric structures, which may be formed by removing gate electrodes in some of the transistors and providing a dielectric material into the openings. The presence of the dielectric structures can further boost the local layout effect.