Template-Based IC Layout Placement for Analog Boundary Constraints

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Solution Overview

Problem

The increasing design complexity and time required for semiconductor layout, particularly in analog circuits, necessitates an automatic layout generation method that can accommodate various boundary conditions while maintaining design preferences.

Innovation Solution

A layout placement method involving the extraction of sub-cells from netlist data, virtual placement of layout elements based on templates, evaluation using a machine learning model, and selective routing to minimize wire length and area, leveraging a template-based approach to automate layout generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If manual layout placement is performed by designing engineers, then design preferences and analog constraints can be considered, but time consumption and efficiency are reduced

Engineering Contradiction:
Improvelayout design qualityVSAvoidlayout design time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-defining multiple template layouts with different configuration options before actual placement. These templates contain pre-configured arrangement patterns for circuit components that can be directly applied, eliminating the need for manual layout design while preserving design quality through evaluated template selection.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes parameters by evaluating multiple template layouts based on different criteria (area, wire length, design rules) and selecting the optimal template. This parameter-based evaluation and selection process automates the decision-making that previously required engineer judgment, maintaining layout quality while reducing time consumption.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If automatic layout generation is implemented, then time efficiency is improved, but adaptability to various boundary conditions and design preferences may be reduced

Engineering Contradiction:
Improvelayout generation speedVSAvoidadaptability to boundary conditions
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The system segments the layout design into multiple independent template options, each representing a different configuration approach. By dividing the design space into discrete templates with varying characteristics, the system can automatically evaluate and select the most appropriate template for specific boundary conditions, maintaining adaptability while enabling automation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements dynamics by making the template selection process adaptive to different boundary conditions. The evaluation mechanism dynamically chooses the most suitable template based on specific design requirements and constraints, allowing the automatic generation system to adapt to various scenarios rather than using a fixed approach.

Inventive Principle:
Principle #15Dynamics

3Manufacturing precision

If multiple template layouts are evaluated and selected based on optimization criteria, then layout quality is improved, but computational complexity increases

Engineering Contradiction:
Improvelayout optimization qualityVSAvoidcomputational complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The system applies partial action by evaluating multiple templates but selecting only the single best option based on optimization criteria. This approach provides sufficient optimization quality by considering multiple possibilities while avoiding the excessive complexity of evaluating all possible layout configurations, achieving a balance between quality and computational effort.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20260080142A1Layout placement method, integrated circuit design method including the same, and integrated circuit design system
Publication Date: 2026.03.19 SAMSUNG ELECTRONICS CO LTD
  • US20260080142A1 patent drawing
  • US20260080142A1 patent drawing
  • US20260080142A1 patent drawing

AI summary

An example method includes extracting a plurality of sub-cells based on netlist data; generating a first plurality of layout elements corresponding to the plurality of sub-cells; performing virtual placement of the first plurality of layout elements to obtain at least one virtually placed layout, the first plurality of layout elements corresponding to a plurality of layout elements that at least one template contains; selecting, based on evaluating the at least one virtually placed layout, a first template from the at least one template; and placing and routing the first plurality of layout elements based on the first template.