IC Layout Thermal Modeling for Redistribution Layer Accuracy
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Solution Overview
Problem
Current IC design processes face challenges in accurately simulating thermal analysis during the manufacturing stage, as existing methods either sacrifice accuracy for speed or vice versa, and fail to account for varying heat dissipation capabilities of off-chip interconnects connected to external circuitry.
Innovation Solution
A thermal analysis method that customizes modeling resolutions for conductive layers based on their properties and assigns distinct boundary conditions to off-chip interconnects based on their connectivity with external circuitry, balancing accuracy and processing time by using different modeling rules for thicker and thinner layers, and varying mesh resolutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If uniform high modeling resolution is applied to all conductive layers, then thermal simulation accuracy is improved, but processing time increases significantly
Solution Approach 1:
The patent applies different modeling resolutions to different conductive layers based on their specific properties. Thicker conductive layers are modeled with lower resolution while thinner layers use higher resolution, allowing the simulation to focus computational resources where they are most needed rather than uniformly across all layers.
Solution Approach 2:
The patent changes the modeling parameters (resolution levels) based on the thickness parameter of each conductive layer. By dynamically adjusting the modeling resolution parameter according to layer thickness, the system achieves optimal balance between accuracy and processing efficiency for each specific layer.
2Device complexity
If single boundary condition is applied to all off-chip interconnects, then model simplicity is maintained, but thermal analysis accuracy deteriorates due to varying heat dissipation capabilities
Solution Approach 1:
The patent assigns different boundary conditions to different off-chip interconnects based on their connectivity characteristics with external circuitry. Each interconnect receives a boundary condition tailored to its specific heat dissipation capability rather than applying a uniform condition to all interconnects.
3Measurement precision
If detailed thermal simulation is performed, then heat distribution prediction accuracy is improved, but computational resources and processing time increase
Solution Approach 1:
The patent applies detailed thermal simulation selectively to thinner conductive layers that require higher resolution modeling, while using simplified models for thicker layers. This localized approach to simulation detail maintains accuracy where needed while preserving overall design process efficiency.
Solution Approach 2:
The patent segments the thermal simulation process by dividing conductive layers into different groups based on thickness characteristics. Each segment is then simulated with appropriate resolution levels, allowing detailed analysis of critical thin layers while using coarser models for thicker layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of thermal simulations while maintaining acceptable processing times, improving the prediction of heat distribution and reducing the risk of overheating issues in IC devices, thereby enhancing reliability and performance.
Implementation Method 1
performing a thermal simulation based on models of a plurality of conductive layers in the redistribution structure
Data Source
AI summary
A system includes a processor for performing a thermal analysis for an IC layout, which includes a redistribution structure having a plurality of conductive layers stacked one upon another in a thickness direction. In response to a property of a first conductive layer satisfying a first condition, the processor applies a first modeling rule to the first conductive layer to obtain a first model, and, in response to the property of a second conductive layer satisfying a second condition but not the first condition, the processor applies a second modeling rule different from the first modeling rule to the second conductive layer to obtain a second model. The processor performs a thermal simulation for the IC layout based on the first and second models, and, based on the thermal simulation result, modifies the IC layout or proceeds with manufacturing one or more IC devices corresponding to the IC layout.