Integrated Circuit Layout Timing Optimization via Derivative Cell Generation
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Solution Overview
Problem
Existing methods for scaling down integrated circuit chip layouts to smaller technology nodes result in process and performance variations, requiring inefficient manual corrections and extensive man-hours to achieve design optimization.
Innovation Solution
A computer program product that generates adjusted electronic representations of integrated circuit layouts by creating full node cells, scaling them to shrink node cells, comparing timing performance, and generating derivative cells to minimize performance differences, thereby optimizing the design process without excessive manual effort.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual engineering change orders are used to correct scaling problems, then design quality can be improved, but the time and effort required increases significantly
Solution Approach 1:
The patent applies preliminary action by performing timing analysis and identifying potential timing violations before the actual tape-out process. The system proactively detects cells that may have timing issues due to scaling effects and prepares correction plans in advance, rather than waiting for manual discovery and correction during implementation.
Solution Approach 2:
The system implements self-service by automatically detecting timing violations and generating corrected netlists without requiring manual intervention. The automated timing analysis and correction process allows the design system to self-correct scaling-induced timing issues, reducing the need for manual engineering change orders while maintaining design quality.
2Area of stationary object
If fixed-factor scaling is applied to shrink chip layouts, then area reduction is achieved, but process and performance variations increase
Solution Approach 1:
The patent applies local quality by performing cell-by-cell timing analysis and applying targeted corrections only to specific cells that exhibit timing violations. Rather than uniformly adjusting all cells, the system identifies individual cells with timing issues and applies localized corrections to those specific cells, maintaining precision while achieving area reduction.
Solution Approach 2:
The system implements parameter changes by dynamically adjusting cell timing parameters based on actual timing analysis results. The automated process modifies timing-related parameters of specific cells to compensate for scaling-induced variations, thereby maintaining performance consistency across the shrunk design without requiring uniform parameter changes across all cells.
3Measurement precision
If automated timing analysis is performed on all cells, then timing performance accuracy improves, but computational complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the timing analysis process into discrete cell-level evaluations. The system segments the overall design into individual cells and performs timing analysis on each cell independently, allowing for precise timing measurement while managing computational complexity through modular, incremental processing of cell groups.
Solution Approach 2:
The system implements partial action by performing timing analysis on cells selectively based on their likelihood to exhibit timing violations. Rather than uniformly analyzing every cell with equal depth, the system focuses computational resources on cells that are more susceptible to timing issues due to scaling effects, achieving sufficient timing accuracy without the full computational burden of exhaustive analysis of all cells.
Data Source
AI summary
An embodiment is a method for providing an adjusted electronic representation of an integrated circuit layout, the method including using one or more processor, generating a timing performance of a path in a first netlist, identifying a first cell in the path that violates a timing performance parameter, and generating a plurality of derivative cells from a subsequent cell that is in the path after the first cell, where each derivative cell includes a variation of the subsequent cell. The method further includes in response to the identifying the first cell, replacing the subsequent cell with at least one of the plurality of derivative cells to generate a first modified netlist, where the variation of the at least one of the plurality of derivative cells reduces the violation of the timing performance parameter, and generating a final netlist based on the first modified netlist.