Integrated Circuit Layout Structure Design for Yield and Reliability
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Solution Overview
Problem
Existing automated circuit design methods often result in integrated circuits prone to failure, leading to decreased yield during manufacturing, as they do not adequately consider design for manufacturing (DFM) and design for yield (DFY) factors such as electromigration, stress, and signal interference.
Innovation Solution
A method and apparatus that compute a layout structure for integrated circuits based on relationships between current parameters, conductor lengths, microstructure cardinality, time-dependent signals, induced stress, and electrical surge parameters, incorporating design principles that account for maximum permissible current densities, slew rates, and localized pulse energies to reduce the likelihood of device failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated placement and routing is performed using conventional EDA tools, then design productivity is improved, but device reliability deteriorates due to susceptibility to failure
Solution Approach 1:
The patent applies preliminary action by computing and evaluating multiple layout structures before final device fabrication. The system generates numerous candidate layouts, evaluates them against failure criteria (electromigration, stress, signal interference), and selects optimized designs in advance, preventing failures before they occur in manufacturing or operation.
Solution Approach 2:
The patent implements feedback by using evaluation functions that assess layout structures against design-for-manufacturing and design-for-yield criteria. The system computes scores based on electromigration risk, stress analysis, and signal interference patterns, then uses this feedback to iteratively improve layout selections, ensuring reliable designs are chosen.
2Ease of manufacture
If conventional placement and routing techniques are used, then manufacturing cost is reduced, but yield deteriorates due to device failure during manufacturing
Solution Approach 1:
The patent applies preliminary action by performing design-for-yield analysis and computing layout structures that anticipate manufacturing failures before they occur. The system evaluates potential failure modes and selects layouts that are robust against manufacturing variations, improving yield without requiring expensive post-manufacturing repairs or rework.
3Reliability
If design constraints for electromigration and stress are incorporated, then device reliability is improved, but design complexity increases
Solution Approach 1:
The patent applies self-service by implementing automated evaluation functions that compute electromigration, stress, and signal interference metrics directly from netlist data. The system automatically generates layout structures that satisfy design-for-manufacturing criteria without requiring manual intervention, making the complexity management transparent and automated rather than adding manual design burden.
4Manufacturing precision
If multiple layout structures are evaluated using evaluation functions, then design precision is improved, but computational time increases
Solution Approach 1:
The patent applies partial or excessive action by computing a limited number of layout structures with the highest predicted success probabilities rather than exhaustively evaluating all possible layouts. The system uses probabilistic modeling to identify and evaluate only the most promising candidates, achieving high design precision with reduced computational time by focusing efforts on the most relevant options.
Data Source
AI summary
Apparatus, methods, and computer readable code for computing parameters related to layout schemes of integrated circuits are disclosed herein. In some embodiments, an actual layout scheme is computed, for example, for a netlist. In some embodiments, one o or more layout schemes are scored based on, for example, susceptibility to failure and/or yield in manufacturing.