Integrated Circuit Leakage Current Reduction via Asymmetric Etching
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Solution Overview
Problem
Integrated circuit structures face increased leakage current when operating at high voltages due to the uniform distance between epitaxial structures and gate stacks in both low and high voltage devices, which affects processing efficiency and power management.
Innovation Solution
The solution involves varying the distance between epitaxial structures and gate stacks in high voltage devices to be significantly greater than in low voltage devices, with a difference in the range of 3 nm to 10 nm, and using an ion-doped layer in the high voltage area to control etching and reduce leakage current through anisotropic etching recesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the distance between epitaxial structures and gate stacks is kept uniform in both low and high voltage devices, then the manufacturing process is simplified, but leakage current increases in high voltage devices
Solution Approach 1:
The patent applies local quality by creating different etching recess depths in different regions of the substrate. Specifically, a first etching recess is formed in the high voltage device region with a greater depth, while a second etching recess is formed in the low voltage device region with a lesser depth. This allows each region to have optimized characteristics for its specific voltage requirements, reducing leakage current in high voltage devices while maintaining standard performance in low voltage devices.
Solution Approach 2:
The patent segments the substrate into distinct high voltage and low voltage device regions, each receiving different etching treatments. The selective formation of etching recesses in different regions creates spatially differentiated structures that address the specific needs of each device type, allowing independent optimization of leakage current characteristics for high voltage devices without affecting low voltage device performance.
2Object-generated harmful factors
If the distance between epitaxial structures and gate stacks is increased in high voltage devices, then leakage current is reduced, but the device area increases
Solution Approach 1:
The patent addresses the area increase problem by transitioning from a two-dimensional uniform distance approach to a three-dimensional solution using etching recesses. By creating deeper recesses in the high voltage device region, the effective distance between epitaxial structures and gate stacks is increased vertically rather than horizontally, thereby reducing leakage current without significantly increasing the planar device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases leakage current in high voltage devices during operation, enhancing the dielectric properties and operational efficiency of integrated circuit structures.
Implementation Method 1
using an ion-doped layer in the high voltage area to control etching and reduce leakage current through anisotropic etching recesses
Data Source
AI summary
An integrated circuit structure is provided including a substrate, a low voltage device and a high voltage device. The low voltage device has a first beeline distance from a first epitaxial structure to an adjacent gate stack; and the high voltage structure has a second beeline distance from a second epitaxial structure to an adjacent gate stack. The second beeline distance of the high voltage device is greater than the first beeline distance of the low voltage device, so that the leakage current in the high voltage device may be decreased under high voltage operation. Further, a method for manufacturing the integrated circuit structure also provides herein.