Integrated Circuit Leakage Optimization via Cell Swapping

The patent applies parameter changes by utilizing multiple threshold voltage libraries (e.g., 1.8V, 2.5V, 3.3V thresholds) to replace standard cells. Each library offers different drive strengths and leakage characteristics. The optimization process selectively swaps cells between these libraries based on timing slack and leakage potential, thereby changing the electrical parameters of the circuit to reduce leakage while maintaining timing requirements.

The patent implements dynamics through an iterative optimization process that dynamically adjusts cell selections. The algorithm repeatedly evaluates timing paths, identifies cells with sufficient slack, and performs swaps with alternative threshold cells. This dynamic adjustment continues until convergence, allowing the design to adaptively find the optimal balance between leakage reduction and timing closure.

The patent merges two previously separate optimization objectives—timing closure and leakage reduction—into a unified optimization process. By integrating leakage awareness into the timing-driven optimization framework, the algorithm simultaneously considers both timing constraints and leakage potential when selecting cells from multiple threshold libraries, achieving both goals concurrently rather than sequentially.

The optimization process changes the selection criteria for standard cells by incorporating leakage metrics alongside timing metrics. Cells are evaluated based on a combination of timing slack and leakage characteristics, and swaps are performed to optimize both parameters simultaneously. This parameter-based selection strategy enables effective leakage reduction without compromising timing closure.

The patent applies local quality by making threshold voltage selections specific to each cell's location and timing context within the circuit. Rather than uniformly applying a single threshold library across the entire design, the optimization process evaluates each cell individually based on its timing slack and local requirements. Cells in timing-critical paths may use lower-threshold (higher drive strength) variants, while cells with sufficient slack use higher-threshold (lower leakage) variants, optimizing both speed and leakage locally.

The patent changes the drive strength parameter of individual cells by selecting from multiple threshold libraries with different characteristics. Lower-threshold cells provide higher drive strength for timing-critical paths, while higher-threshold cells reduce leakage in non-critical paths. This parameter variation across different cells enables the circuit to achieve timing requirements while minimizing overall leakage current.