Single-Level IC Interconnects With Line Breaks and Bridges
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Solution Overview
Problem
The challenge in integrated circuits (ICs) is to achieve scaled-down geometries for conductive interconnects without increasing costs, as current lithographic processes struggle with extremely small critical dimensions and pitches, often requiring multiple patterning processes that are costly and inefficient.
Innovation Solution
The implementation of a single-mask level technique using pitch-splitting patterning to define line breaks and line bridges, allowing for the fabrication of interconnect structures with reduced mask count and increased density, by employing a lithographic plate or reticle that prints photoresist mask structures at a given pitch, and using a grating mask structure to pattern conductive traces within a dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithographic masks are used in a multiple patterning process to form conductive interconnect traces with extremely small critical dimensions and pitches, then the resolution capability is improved, but the manufacturing cost increases dramatically
Solution Approach 1:
The patent segments the interconnect structure into distinct components: conductive traces and dielectric plugs. The plugs are strategically positioned to enable pitch multiplication, allowing a single lithographic mask to define features at effective pitches smaller than the mask's native resolution limit. This segmentation approach resolves the contradiction by achieving high precision through structural design rather than relying on multiple expensive masking steps.
Solution Approach 2:
The patent introduces vertical dimensionality through dielectric plugs that extend between conductive traces at different levels. These plugs create effective pitch reduction by utilizing the third dimension (vertical spacing) to achieve horizontal pitch multiplication. This dimensional transition allows single-mask fabrication of features that would otherwise require multiple patterning passes, thereby reducing cost while maintaining precision.
2Area of stationary object
If the pitch of conductive traces is reduced to increase device density, then the area occupied by interconnects is reduced, but the lithographic resolution capability becomes insufficient
Solution Approach 1:
The patent introduces dielectric plugs as intermediary structures that mediate between the lithographic mask and the final conductive trace pattern. These plugs act as self-aligned registration features that enable pitch multiplication, allowing the lithographic system to effectively resolve smaller pitches without requiring the mask itself to have higher resolution. The intermediary plugs bridge the gap between mask capability and desired trace density.
Solution Approach 2:
The patent changes the effective pitch parameter through the introduction of dielectric plugs with specific dimensional relationships. By controlling the spacing and dimensions of these plugs relative to the conductive traces, the effective pitch between trace features is reduced without changing the actual lithographic mask pitch. This parameter transformation allows high-density interconnects to be fabricated with existing lithographic tools.
3Manufacturing precision
If multiple lithographic masks are used to achieve small critical dimensions, then the manufacturing precision is improved, but the process complexity increases
Solution Approach 1:
The patent merges the functions of multiple lithographic masks into a single mask by incorporating plug definition features directly into the mask design. Instead of requiring separate masking steps for traces and plugs, both features are defined simultaneously in one exposure step. This merging of operations reduces process complexity while maintaining the manufacturing precision needed for small critical dimensions through the pitch-splitting methodology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the need for multiple lithographic masks, decreases overlay tolerances, and increases interconnect density, enabling the fabrication of complex damascene-type interconnect structures at scaled-down geometries while minimizing costs.
Implementation Method 1
employing a lithographic plate or reticle that prints photoresist mask structures at a given pitch
Implementation Method 2
an opening for the trench may be etched in the dielectric layer by using the photoresist layer as an etch mask
Data Source
AI summary
Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.