IC Logic Layout With Three Power Rails for Shorter Conductive Paths
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Solution Overview
Problem
The ongoing trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices that consume less power but face challenges in maintaining speed and reliability due to increased electromigration risks associated with longer conductive segment lengths.
Innovation Solution
The implementation of an IC device configuration that includes three power rails and a plurality of transistors with four active areas, gates, and conductive segments extending across the middle power rail, reducing conductive segment lengths and thereby mitigating speed degradation and electromigration-based reliability risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of power rails is reduced to two, then device complexity is reduced, but conductive segment lengths increase causing speed degradation and electromigration risks
Solution Approach 1:
The power distribution network is segmented into three distinct power rails instead of using a traditional two-rail configuration. This segmentation allows conductive segments to span shorter distances between adjacent power rails, reducing signal transmission length and improving speed while maintaining manageable device complexity through systematic layout organization.
2Device complexity
If the number of power rails is reduced to two, then device complexity is reduced, but electromigration risks increase due to longer conductive segments
Solution Approach 1:
By dividing the power distribution into three separate rails, the conductive path length between power supply points is halved compared to a two-rail system. This segmentation reduces the current density and stress on individual conductive segments, thereby mitigating electromigration risks and improving overall device reliability without significantly increasing complexity.
3Area of stationary object
If conductive segment lengths are increased, then device area is reduced, but speed degradation occurs
Solution Approach 1:
The patent transitions from a conventional two-dimensional layout optimization to a three-dimensional power rail configuration. By adding the vertical dimension of a third power rail, the system achieves shorter conductive segment lengths without necessarily increasing the planar device area, as the third rail provides additional spatial pathways for signal routing.
Data Source
AI summary
An IC device includes first and second power rails extending in a first direction and carrying one of a power supply or reference voltage, a third power rail extending between the first and second power rails and carrying the other of the power supply or reference voltage, and a plurality of transistors including first through fourth active areas extending between the first and second power rails, a plurality of gate structures extending perpendicularly to the first direction, and first and second conductive segments extending in the second direction across the third power rail. Each of the second and third active areas is adjacent to the third power rail, each of the first and second conductive segments is electrically connected to S/D structures in each of the second and third active areas, and the plurality of transistors is configured as one of an AOI, an OAI, or a four-input NAND gate.