IC Loopback BIST for Clock Skew and PVT Variation Profiling
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Solution Overview
Problem
Differences in clock signal arrival times across components in semiconductor integrated circuits can lead to performance errors due to synchronization issues.
Innovation Solution
A built-in self-test (BIST) circuit with a test circuit connected to the first circuit, utilizing a controller, multiplexer, frequency counter, and loopback paths to measure oscillation frequencies and generate an on-chip variation profile, accounting for process, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock tree is used to distribute clock signals to various components, then synchronization of operation is achieved, but differences in arrival time of clock signals at different components still occur causing performance errors
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple loopback paths with different lengths before operation. These paths are prepared in advance to account for process, voltage, and temperature variations, allowing the system to select the appropriate path without real-time adjustment delays.
Solution Approach 2:
The patent implements dynamics by making the loopback path selection adaptive and variable. The system dynamically chooses among multiple loopback paths based on measured oscillation frequencies, allowing the feedback path to adjust to changing operating conditions and maintain measurement accuracy.
2Measurement precision
If additional bond pads are used to improve measurement resolution, then measurement precision improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies universality by designing loopback paths that serve multiple functions: they provide feedback for oscillation frequency measurement, enable process-voltage-temperature variation characterization, and allow for different measurement resolutions without requiring separate dedicated structures for each function.
Solution Approach 2:
The patent implements nesting by creating hierarchical loopback paths where shorter paths are nested within longer paths. This allows the same physical structure to provide multiple measurement resolutions, with the ability to select between coarse and fine measurement modes without adding separate bond pads.
3Adaptability or versatility
If loopback paths with different lengths are used to account for PVT variations, then adaptability improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the feedback path into multiple discrete loopback paths with different lengths. Each path is segmented to provide specific PVT compensation characteristics, allowing the system to select the appropriate segment based on operating conditions rather than using a single complex adjustable path.
Data Source
AI summary
An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback path. The circuit is configured to receive a first voltage signal that is either a substantially low logic level signal or a substantially high logic level signal. The circuit is configured to generate an oscillating signal from the first voltage signal, and the counter is configured to count oscillations of the oscillating signal.