Hot Spot Detection in IC Masks via Simulation and Aerial Images
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Solution Overview
Problem
Current methods in integrated circuit manufacturing struggle to detect and correct hot spots, which are regions with marginally acceptable process windows that can lead to yield-limiting defects due to variations in mask and wafer patterning processes, as existing metrology tools lack the sensitivity and comprehensive sampling needed to identify and address these issues effectively.
Innovation Solution
A method that combines high-speed simulation with massive data collection from aerial images to identify, classify, and prioritize hot spots, using a combination of simulation-based systems and aerial image inspection to determine necessary process corrections and optimize RET implementation for improved yield and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional metrology tools are used to detect hot spots, then the inspection process is simple, but the detection precision and sensitivity are insufficient to identify marginally acceptable patterns
Solution Approach 1:
The inspection process is segmented into multiple specialized stages: simulation-based hot spot identification, aerial image data collection, statistical sampling analysis, and corrective action implementation. Each stage uses targeted tools and methods appropriate to that specific function, allowing high precision detection without requiring a single overly complex monolithic system.
Solution Approach 2:
The simulation step performs preliminary identification of potential hot spots before actual aerial image collection. This pre-screening process identifies regions with marginally acceptable process windows, allowing the subsequent inspection to focus resources on critical areas rather than examining the entire mask uniformly, thereby improving detection sensitivity while managing complexity.
2Reliability
If comprehensive sampling of the entire mask is performed, then all hot spots are detected, but the inspection time and productivity are reduced
Solution Approach 1:
The simulation process performs preliminary identification and classification of hot spots before physical inspection. By pre-identifying regions with marginally acceptable process windows and calculating their severity, the system can then apply statistical sampling methods that focus measurement resources on the most critical areas, achieving reliable detection without requiring exhaustive inspection of every mask region.
Solution Approach 2:
The system changes the parameter of sampling density based on hot spot severity classification. Critical hot spots receive higher sampling density and more rigorous inspection, while less critical regions use reduced sampling. This parameter adaptation allows the system to maintain high reliability for detecting yield-limiting defects while improving overall inspection throughput through intelligent resource allocation.
3Reliability
If the mask pattern is corrected to eliminate hot spots, then yield improves, but the manufacturing complexity and cost increase
Solution Approach 1:
The system applies corrections locally only to identified hot spot regions rather than redesigning the entire mask. By targeting specific patterns with marginally acceptable process windows and applying localized RET techniques or geometry modifications, the system improves yield in critical areas while leaving the rest of the mask unchanged, thereby reducing overall manufacturing complexity compared to global redesign approaches.
Solution Approach 2:
The simulation creates a virtual model of the lithography process and mask patterns to identify hot spots before physical mask fabrication. This digital copying and testing allows correction identification in the virtual domain, reducing the risk and complexity of iterative physical mask revisions. Once corrections are validated in simulation, they can be applied to the actual mask with greater confidence and reduced manufacturing complexity.
Data Source
AI summary
One embodiment of a method for detecting, sampling, analyzing, and correcting hot spots in an integrated circuit design allows the identification of the weakest patterns within each design layer, the accurate determination of the impact of process drifts upon the patterning performance of the real mask in a real scanner, and the optimum process correction, process monitoring, and RET improvements to optimize integrated circuit device performance and yield. The combination of high speed simulation coupled with massive data collection capability on actual aerial images and/or resist images at the specific patterns of interest provides a complete methodology for optimum RET implementation and process monitoring.