IC Mask Patterning for Sub-45nm Feature Accuracy
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Solution Overview
Problem
Current optical proximity correction (OPC) techniques are insufficient for sub-45 nm technology nodes, leading to inaccurate or poorly shaped device features in semiconductor integrated circuits, which affect device performance.
Innovation Solution
The method involves modifying the IC design layout by adding assist features and performing iterative optical proximity correction and mask rule checking to ensure that the final pattern on the wafer meets design rules, using a combination of optical proximity correction, mask rule checking, and photolithography simulation to refine the design and correct for manufacturing limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current OPC techniques are used for sub-45 nm designs, then the manufacturing process can be maintained, but the device features become inaccurate or poorly shaped
Solution Approach 1:
The patent applies preliminary action by performing optical proximity correction on the mask design before fabrication. The OPC process pre-compensates for expected distortion by modifying the mask pattern to account for optical effects that will occur during lithography. This includes adding assist features and adjusting feature dimensions in advance to counteract rounding, pinching, and other distortions that would otherwise degrade device feature accuracy at sub-45 nm nodes.
2Productivity
If geometry size is decreased to increase functional density, then production efficiency increases, but feature shape accuracy deteriorates
Solution Approach 1:
The patent applies local quality by applying different correction strategies to different regions of the mask design. The OPC process analyzes local feature characteristics and applies targeted corrections to specific problem areas such as corners prone to rounding, narrow spaces prone to pinching, and regions with varying density. This localized approach ensures that corrections are applied where needed without unnecessarily complicating the entire mask design.
Solution Approach 2:
The patent applies preliminary action by performing optical proximity correction on the mask design before fabrication. The OPC process pre-compensates for expected distortion by modifying the mask pattern to account for optical effects that will occur during lithography. This includes adding assist features and adjusting feature dimensions in advance to counteract rounding, pinching, and other distortions that would otherwise degrade device feature accuracy at sub-45 nm nodes.
3Manufacturing precision
If OPC is performed to correct feature distortion, then feature accuracy improves, but the complexity of the mask design increases
Solution Approach 1:
The patent applies partial or excessive action by selectively applying OPC corrections only to features that require them, rather than uniformly complicating the entire mask design. The process identifies specific problem areas such as corners, narrow spaces, and high-density regions, and applies corrections only to those locations. This selective approach achieves the necessary feature accuracy while minimizing the overall increase in mask design complexity.
Data Source
AI summary
Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.