IC-Memory Interface Switching for No-Clock Data Access
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Solution Overview
Problem
Existing electronic parts with integrated circuits face inaccessibility issues when the clock source is not operational, preventing external apparatuses from writing and reading data from the memory.
Innovation Solution
The electronic part includes an integrated circuit with a first and second interface circuit that switches between communication states based on the clock signal, allowing access to the memory even when the clock source is not operational, using a control circuit to manage communication states and enable data access through I2C communication protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock source is implemented in the integrated circuit, then normal operation and data processing are enabled, but the memory becomes inaccessible when the clock source is not operational
Solution Approach 1:
The interface circuit dynamically switches between two communication modes: a first mode for normal operation when the clock source is active, and a second mode for memory access when the clock source is inactive. This dynamic adaptation allows the system to maintain memory accessibility regardless of clock source operational status.
Solution Approach 2:
The system changes the operational parameters of the interface circuit based on clock source status. When the clock source is not operational, the interface circuit transitions to an alternative communication protocol or timing scheme that does not depend on the internal clock, thereby enabling memory access under varying operational conditions.
2Productivity
If the integrated circuit uses an internal clock source, then processing operations are streamlined, but external apparatus cannot access memory without the clock operating
Solution Approach 1:
The interface circuit serves as an intermediary between the external apparatus and the memory. It mediates communication by supporting multiple operational modes, including a second mode that enables direct memory access from external apparatus without requiring the internal clock source to be operational, thus facilitating ease of external access.
Solution Approach 2:
The interface circuit is designed with multi-functionality to handle both normal processing operations (first mode) and external memory access operations (second mode). This universal design allows the same interface circuit to efficiently support data processing when the clock is active and external memory access when the clock is inactive.
3Stability of the object's composition
If the electronic part requires a clock source for operation, then internal processing is synchronized, but the system cannot operate or access memory without it
Solution Approach 1:
The interface circuit dynamically adapts its operational mode based on the presence or absence of clock signals. When clock signals are present, it operates in the first mode with synchronized processing. When clock signals are absent, it switches to the second mode that maintains memory accessibility without synchronization requirements, ensuring system reliability under varying conditions.
Solution Approach 2:
The system utilizes periodic clock signals when available to synchronize internal processing operations. However, the interface circuit is designed to function without these periodic signals by switching to an alternative mode that does not rely on periodic timing, thereby maintaining accessibility even when periodic synchronization is not available.
Data Source
AI summary
An electronic part including an integrated circuit and a memory, the integrated circuit including a first clock terminal to which a clock signal is inputted, a first data terminal via which a first serial data signal is inputted and outputted, a second clock terminal via which the clock signal is outputted to the memory, a second data terminal via which a second serial data signal is inputted and outputted from and to the memory, and a first interface circuit including a control circuit that controls the communication state of the integrated circuit to be a first communication state in which the first serial data signal inputted to the first data terminal is outputted as the second serial data signal via the second data terminal or a second communication state in which the second serial data signal inputted to the second data terminal is outputted as the first serial data signal via the first data terminal.