IC Memory Timing Regulation via Pulse Signal Feedback
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Solution Overview
Problem
Integrated circuit memory devices face performance degradation due to unstable timing characteristics, which are sensitive to operating environment variations, leading to errors in data read and write operations, especially as operating speed increases.
Innovation Solution
A timing measurement signal generator and regulating device/method that measure and control timing gaps between control signals by generating pulse signals representing timing gaps between specific control signals, such as word line enable and bit line sensing enable, column select line enable and first read pulse, and word line disable and bit line equalizing signals, and adjust these signals to maintain predetermined timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of the integrated circuit memory device is increased, then the productivity is improved, but the timing characteristics become increasingly sensitive to operating environment variations, leading to errors in data operations
Solution Approach 1:
The patent implements a feedback mechanism by generating a timing measurement signal that monitors the actual timing gaps between control signals. This measurement signal is fed back to a timing regulating device that adjusts the timing of control signals to maintain predetermined timing gaps, thereby compensating for environmental variations and ensuring stable operation at high speeds
Solution Approach 2:
The patent replaces manual or external timing adjustment mechanisms with an automated electronic system. The timing measurement signal generator and timing regulating device form an electronic control system that automatically measures and adjusts timing gaps, eliminating the need for mechanical timing devices or external calibration
2Device complexity
If the timing gap between control signals is not precisely controlled, then the device complexity is reduced, but the reliability of data read and write operations deteriorates due to errors caused by poor timing characteristics
Solution Approach 1:
The timing measurement signal generator and timing regulating device form a self-contained system that automatically measures timing gaps and regulates control signal timing without external intervention. The system uses internal pulse generators and logic circuits to generate measurement signals and perform timing adjustments, making the device self-sufficient in maintaining timing accuracy
Solution Approach 2:
The patent introduces a timing measurement signal as an intermediary element that bridges the gap between control signal generation and timing verification. This measurement signal acts as a mediator that carries timing information from the control signals to the regulation mechanism, enabling precise timing control without direct complex interconnections
Data Source
AI summary
A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination. For example, the pulse signal may be a timing measurement signal including a first pulse signal representing a first timing margin between a word line enable signal and a bit line sensing enable signal, a second pulse signal representing a second timing margin between a column select line enable signal and a first read pulse signal, and a third pulse signal representing a third timing margin between a word line disable signal and a bit line equalizing signal. Related devices are also discussed.