Balancing Parasitic Capacitances in IC Metal Tracks

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Solution Overview

Problem

Imbalanced parasitic capacitance in integrated circuit chips affects the AC common-mode rejection ratio (CMRR) performance, leading to degraded performance at higher frequencies, which can only be measured after fabrication, resulting in costly and time-consuming redesigns.

Innovation Solution

The method involves attaching additional detachable structural metal elements, such as tab capacitors, to the metal tracks during fabrication and selectively detaching them to balance parasitic capacitance, using techniques like laser trimming or fuse opening, to optimize AC CMRR performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If additional metal elements are attached to metal tracks during fabrication, then parasitic capacitance balancing capability is improved, but device complexity increases

Engineering Contradiction:
Improveparasitic capacitance balancingVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The solution segments the capacitance balancing function into multiple detachable metal elements (first additional metal element, second additional metal element, etc.) that can be independently controlled. Each metal element is selectively detached or retained to achieve the desired capacitance balance, transforming a monolithic design problem into a modular configuration problem.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces dynamic configurability to the circuit design by making metal elements detachable after fabrication. The system transitions from a static fixed design to a dynamic reconfigurable system where the capacitance balance can be adjusted by selectively removing specific metal elements based on measured performance.

Inventive Principle:
Principle #15Dynamics

2Reliability

If layout changes are made after fabrication to improve AC CMRR performance, then performance is improved, but time and cost increase

Engineering Contradiction:
ImproveAC CMRR performanceVSAvoidredesign time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The invention performs preliminary action by pre-attaching multiple additional metal elements to the circuit during the initial fabrication process. These elements are prepared in advance with detachable connections, enabling future adjustments without requiring complete redesign or remanufacturing of the entire device.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The solution enables parameter changes in the capacitance characteristics by selectively detaching specific metal elements. This allows continuous adjustment of the parasitic capacitance values to optimize AC CMRR performance, transforming fixed parameters into可调 parameters without changing the fundamental circuit architecture.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If parasitic capacitance is directly measured to balance inputs, then measurement precision is improved, but measurement accuracy deteriorates due to instrument-induced parasitic capacitance

Engineering Contradiction:
Improvecapacitance measurement capabilityVSAvoidparasitic capacitance balance accuracy
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The invention introduces additional metal elements as intermediary components that mediate between the measurement system and the actual parasitic capacitance. These intermediaries provide known, controllable capacitance values that can be selectively added or removed, allowing indirect balancing of the total parasitic capacitance without requiring direct measurement of the problematic capacitance itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for efficient balancing of parasitic capacitances before fabrication, improving AC CMRR performance and reducing the need for post-fabrication redesigns by determining the optimal detachment pattern of additional metal elements to match ideal output curves.

Implementation Method 1

selectively detaching them to balance parasitic capacitance, using techniques like laser trimming or fuse opening

Methodology Applied
Scientific EffectLaser trimming: Laser Ablation

Data Source

PatentUS9966925B2Apparatus and method to balance the parasitic capacitances between metal tracks on an integrated circuit chip
Publication Date: 2018.05.08 ANALOG DEVICES INC
  • US9966925B2 patent drawing
  • US9966925B2 patent drawing
  • US9966925B2 patent drawing

AI summary

Embodiments of the present disclosure provide apparatuses and methods for balancing parasitic capacitances between metal tracks in an integrated circuit chip. Specifically, additional capacitances in the form of, for example, tab capacitors, are attached to the metal tracks with the intention of detaching a select number of the attached capacitances for the purpose of balancing the parasitic capacitances between the metal tracks. The attached capacitances may be structural metal elements. Further, the attached structural metal elements may be detachable at thin-film resistive material associated with each of the attached structural metal elements.