IC Layout Metal Fill Using Timing Slack Stealing
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Solution Overview
Problem
Existing integrated circuit (IC) design methods face challenges in optimizing metal density fill to avoid excessive impact on signal path nets and logic shapes, leading to wasted power and performance issues due to added capacitance from metal fill shapes.
Innovation Solution
Implementing a timing slack stealing aware fill optimization process that identifies and distributes excess timing slack across signal path nets to minimize the impact of metal fill shapes on signal timing characteristics while maintaining sufficient metal density, using techniques such as cross-latch and cross-hierarchy slack stealing aware fill optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metal fill shapes are added to satisfy density requirements, then metal density is improved, but signal timing characteristics deteriorate due to excessive capacitance
Solution Approach 1:
The patent applies local quality by differentiating between critical and non-critical signal path nets based on timing slack. Metal fill shapes are selectively inserted or excluded in specific local regions: excluded from areas surrounding critical nets with low timing slack, and permitted or encouraged in areas surrounding non-critical nets with excess timing slack. This localized approach allows metal density requirements to be met in non-critical regions while preserving signal timing characteristics in critical regions.
2Quantity of substance
If metal fill shapes are added to satisfy density requirements, then metal density is improved, but power efficiency deteriorates due to excessive capacitance
Solution Approach 1:
The patent applies local quality by making power efficiency considerations local to each signal path net based on its timing slack characteristics. By analyzing the timing slack of individual nets and making localized decisions about metal fill insertion, the method reduces capacitance on power-sensitive critical paths while maintaining density in less sensitive areas, thereby improving overall power efficiency without sacrificing density requirements.
Data Source
AI summary
Integrated circuit (IC) design based on timing slack according to an example includes accessing physical design data for an IC layout, wherein the physical design data comprises a netlist including active metal shapes of a metal shapes infrastructure forming signal path nets connecting different parts of the IC layout. Timing-based design rule checking of the physical design data is performed to identify slack stealing information for the signal path nets. Shape-based density design rule checking of the metal shapes infrastructure is performed, based on the slack stealing information, to perform fill insertion of metal fill shapes to satisfy density requirements in the IC layout.