IC Metal Line Layout Segmentation for Simpler Mask Patterning

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Solution Overview

Problem

The complexity of patterning templates in integrated circuit manufacturing is high, leading to increased costs and time due to frequent and complex modifications during the circuit design process, particularly when adjusting metal line arrangements.

Innovation Solution

A method is introduced where the peripheral areas of an integrated circuit layout are kept unchanged during metal line adjustments, while the center areas undergo perimeter adjustments, using an electronic design automation system to simplify the photolithography mask and reduce the likelihood of manufacturing defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If metal line arrangements are frequently modified during circuit design, then circuit functionality is improved, but patterning template complexity increases and manufacturing costs increase

Engineering Contradiction:
Improvecircuit functionalityVSAvoidpatterning template complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The layout is divided into a first area and a second area, where the first area contains metal lines with fixed arrangements that define the patterning template, and the second area contains metal lines that can be freely arranged. This segmentation allows circuit functionality to be modified in the second area without changing the patterning template defined by the first area, thus resolving the contradiction between adaptability and template complexity.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If metal line arrangements are frequently modified during circuit design, then circuit functionality is improved, but manufacturing time increases

Engineering Contradiction:
Improvecircuit functionalityVSAvoidmanufacturing time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

By segmenting the layout into fixed first area and flexible second area, the patterning template associated with the first area remains constant throughout the design process. This eliminates the need to repeatedly modify the patterning template when adjusting metal lines in the second area, significantly reducing manufacturing preparation time while maintaining circuit adaptability.

Inventive Principle:
Principle #1Segmentation

3Reliability

If metal line perimeters are adjusted to improve circuit performance, then circuit reliability is improved, but photolithography mask complexity increases

Engineering Contradiction:
Improvecircuit reliabilityVSAvoidphotolithography mask complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Different regions of the layout are assigned different properties: the first area has fixed metal line arrangements that define the photolithography mask, while the second area allows perimeter adjustments for reliability optimization. This local differentiation enables circuit reliability improvement through metal line adjustments without increasing mask complexity, as the mask is determined solely by the fixed first area.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11748550B2Integrated circuit with constrained metal line arrangement
Publication Date: 2023.09.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11748550B2 patent drawing
  • US11748550B2 patent drawing
  • US11748550B2 patent drawing

AI summary

A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.