Integrated Circuit Metal Routing with 2D Arrangement
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Solution Overview
Problem
Conventional integrated circuits formed using 16 nm or 14 nm process node technology require double patterning for each metal layer, increasing fabrication costs and limiting component density due to stricter design rules for contacted poly pitch (CPP) and metal pitch.
Innovation Solution
Integrated circuits with reduced CPP and metal pitch are developed using a single patterning process for metal layers, incorporating fin field-effect transistors (FinFETs) and a high-k/metal gate (HK/MG) last process, allowing for two-dimensional routing arrangements in metal-1 layers and relaxing design constraints to include additional metal connections in the same layer, thereby reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning process is used to form each metal layer in 16 nm or 14 nm technology, then manufacturing precision is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent segments the metal layer formation into distinct pitch ranges: metal pitch >= 90 nm formed by single patterning, and metal pitch < 90 nm formed by double patterning. This segmentation allows the majority of metal layers to use simpler single patterning while maintaining precision only where necessary.
Solution Approach 2:
The patent changes the metal pitch parameter to determine the patterning method. By designing metal pitches >= 90 nm where possible, the process transitions from requiring double patterning to single patterning, reducing complexity while maintaining acceptable precision through relaxed design rules.
2Productivity
If contacted poly pitch is reduced to increase component density, then productivity is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The patent introduces two-dimensional routing arrangements in metal-1 layers, allowing connections to be made in multiple directions rather than constrained to single-direction routing. This dimensional freedom compensates for reduced contacted poly pitch and relaxes manufacturing precision requirements.
Solution Approach 2:
The patent implements dynamic routing strategies where metal lines can change direction and layer transitions are optimized based on local density requirements. This dynamic approach allows flexible accommodation of reduced pitch dimensions without rigid precision constraints.
3Productivity
If metal pitch is reduced to increase density, then productivity is improved, but device complexity increases due to stricter design rules
Solution Approach 1:
The patent segments design rules into different categories: relaxed rules for metal pitch >= 90 nm allowing single patterning, and stricter rules for metal pitch < 90 nm requiring double patterning. This segmentation enables high density in critical areas while maintaining simplicity elsewhere.
Solution Approach 2:
The patent applies different design rule qualities to different regions of the circuit. High-density regions with metal pitch < 90 nm receive enhanced manufacturing attention and double patterning, while lower-density regions use relaxed single patterning rules, optimizing the overall balance between density and complexity.
Data Source
AI summary
In a particular aspect, an integrated circuit includes a first transistor including a first source region and a first drain region. The integrated circuit includes a second transistor including a second source region and a second drain region. The integrated circuit includes a first gate structure coupled to the first transistor and to the second transistor. The first gate structure is included in a first layer. The integrated circuit further includes a first metal line coupled to the first source region and to the second drain region. The first metal line has a two-dimensional routing arrangement and is included in a second layer that is distinct from the first layer.