Integrated Circuit Metal Routing via Double Patterning

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Solution Overview

Problem

The increasing density of integrated circuits (ICs) poses challenges in design and fabrication due to the complexity of routing conductive traces, leading to difficulties in achieving efficient packing density and reducing manufacturing errors.

Innovation Solution

Implementing a system and method for layout design that routes all metal lines in one direction on each metal layer, utilizing double patterning to increase packing efficiency and relax pitch requirements, thereby enhancing the regularity of metal structures and reducing the risk of manufacturing errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If increasing IC density is implemented, then speed and functionality are improved, but design and fabrication complexity increases

Engineering Contradiction:
ImproveIC densityVSAvoiddesign and fabrication complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the metal line routing into two separate photolithographic patterning steps (first and second photomasks). This allows the complex dense routing to be broken down into manageable segments that can be fabricated with standard pitch requirements, thereby enabling higher IC density without proportionally increasing fabrication complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension by using sequential patterning steps. Instead of attempting to pattern all metal lines in a single step, the process uses two separate photolithography steps taken at different times, allowing complex routing to be achieved through time-based separation of the patterning operations

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If conventional single photomask patterning is used, then fabrication process is simple, but pitch requirements are stringent and packing density is limited

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidpacking density
Core Design Contradiction:
Ease of manufactureVSArea of moving object

Solution Approach 1:

The fabrication process is segmented into two separate photolithography patterning steps using first and second photomasks. This segmentation relaxes the pitch requirements for each individual mask, allowing standard fabrication processes to achieve higher overall packing density that would be impossible with single-mask patterning

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first photomask pattern is formed as a preliminary step before the second photomask pattern. This preliminary action establishes part of the metal line routing, allowing the second patterning step to complete the dense routing configuration with relaxed pitch constraints

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11694013B2Integrated circuit and method of manufacturing same
Publication Date: 2023.07.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11694013B2 patent drawing
  • US11694013B2 patent drawing
  • US11694013B2 patent drawing

AI summary

An integrated circuit includes a first and a set of conductive traces, and a first conductive feature. The second set of conductive traces includes a first conductive trace of the second set of conductive traces corresponding to a gate terminal of a first p-type transistor, and a second conductive trace of the second set of conductive traces corresponding to a gate terminal of a first n-type transistor. The first conductive feature corresponds to at least a first contact of a first dummy transistor. The first conductive trace of the second set of conductive traces is electrically coupled to the second conductive trace of the second set of conductive traces by at least the first conductive feature. The first n-type transistor being part of a first transmission gate. The first p-type transistor being part of a second transmission gate.