Integrated Circuit Metal Layout With Fewer Routing Tracks
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Solution Overview
Problem
Existing integrated circuit designs face challenges in optimizing metal routing to achieve faster processing speeds and lower power consumption within limited area.
Innovation Solution
The proposed solution involves optimizing the layout design of integrated circuits by reducing the number of metal routing tracks and layers, while maintaining effective connectivity between components, through innovative arrangements of conductive patterns, gates, and vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional metal routing designs are used, then connectivity between components is maintained, but the number of metal routing tracks and layers increases, leading to larger layout area and reduced processing speed
Solution Approach 1:
The patent utilizes multiple metal layers (vertical dimension) to route signals, allowing routing paths to transition between layers via vias. This dimensional approach enables complex connectivity without increasing the horizontal footprint, thereby improving processing speed while controlling layout area and reducing the apparent complexity of routing tracks.
Solution Approach 2:
The conductive patterns are designed to serve multiple functions: they act as both signal routing paths and as structural elements that define transistor regions. By making the metal layers multi-functional, the design reduces the need for separate dedicated routing tracks, thereby decreasing the number of metal routing layers while maintaining effective connectivity.
2Reliability
If more metal routing layers are added to improve connectivity, then connectivity between components is enhanced, but the layout area increases and power consumption increases
Solution Approach 1:
The patent employs multiple metal layers stacked vertically to provide redundant and alternative routing paths for signals. This vertical stacking enables enhanced connectivity and reliability without expanding the horizontal layout area, as the additional routing capacity is achieved through the z-dimension rather than spreading out in the x-y plane.
Solution Approach 2:
The conductive patterns are nested within and between transistor structures, with metal layers positioned above and below active regions. This nesting allows routing paths to be embedded within the device structure itself, providing multiple connectivity paths without requiring additional external routing space, thus maintaining compact layout area while improving reliability.
3Productivity
If conventional routing layouts are used, then design simplicity is maintained, but metal resource efficiency is low and processing speed is reduced
Solution Approach 1:
Each metal layer is designed to perform multiple routing functions simultaneously, carrying different signals and providing alternative paths. This multi-functionality maximizes the utilization of metal materials, as each layer contributes to multiple connectivity requirements, thereby improving metal resource efficiency and enabling faster processing without requiring excessive metal quantity.
Solution Approach 2:
The patent distributes routing functions across multiple vertical layers, allowing signals to be routed in three dimensions rather than confined to a single plane. This approach increases metal resource efficiency by utilizing the vertical space above and below the substrate, thereby achieving faster processing speeds with optimized metal usage rather than excessive horizontal expansion.
4Area of stationary object
If the number of metal routing tracks is reduced to improve area efficiency, then layout area is reduced, but connectivity and power efficiency may be compromised
Solution Approach 1:
The patent compensates for the reduction in horizontal routing tracks by utilizing the vertical dimension through multiple metal layers. Signals that would require additional horizontal tracks are instead routed through stacked layers, maintaining connectivity and power efficiency while achieving compact layout area through vertical integration of routing paths.
Solution Approach 2:
Multiple routing paths are nested within the vertical structure of the device, with conductive patterns positioned at different heights. This nesting allows the design to maintain rich connectivity and power distribution capabilities while using fewer horizontal tracks, as the routing capacity is embedded within the vertical architecture rather than requiring lateral expansion.
Data Source
AI summary
A method is provided, and including operations as below: forming multiple active areas extending in a first direction; forming multiple conductive patterns extending in a second direction different from the first direction and arranged in a first layer above the active areas; forming multiple gates extending parallel to the conductive patterns; and forming a first set of conductive lines extending in the first direction and arranged in three first metal tracks that are in a second layer above the first layer, wherein one of the first set of conductive lines is arranged in a middle track of the three first metal tracks, coupled to one of the gates and overlap a first shallow trench region between two of the active areas.