IC Metallization Layout With Horizontal Tracks for 4-Track Routability

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Solution Overview

Problem

The challenge of further minimizing and scaling the poly pitch in integrated circuits is hindered by the reduction in metal track lines per standard cell, leading to issues with routability due to high pin density, low pin accessibility, and limited routing resources.

Innovation Solution

A method for forming integrated circuits that involves creating a standard cell with a 'four tracks' height by arranging metal track lines horizontally instead of vertically, using self-aligned conductive vias to connect electrically conductive lines, and employing a hard mask to ensure precise alignment and etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the cell height is reduced to minimize standard cell size, then the area of the standard cell is reduced, but the number of metal track lines per standard cell is reduced, leading to poor routability

Engineering Contradiction:
Improvestandard cell areaVSAvoidroutability
Core Design Contradiction:
Area of stationary objectVSAdaptability or versatility

Solution Approach 1:

The patent transitions from vertical metal track arrangement to horizontal metal track arrangement within the standard cell. By changing the orientation dimension of metal tracks from vertical to horizontal, the invention enables more efficient use of routing resources while maintaining reduced cell height, thus improving routability without sacrificing area reduction benefits

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention segments the metal routing into multiple horizontal layers (first metallization level, second metallization level) with dedicated vertical connections. This segmentation allows independent optimization of horizontal routing and vertical connections, enabling complex routing patterns to be achieved through coordinated use of multiple segmented routing resources

Inventive Principle:
Principle #1Segmentation

2Productivity

If the poly pitch is minimized to scale down integrated circuits, then the integration density is improved, but the manufacturing complexity increases due to high pin density and limited routing resources

Engineering Contradiction:
Improveintegration densityVSAvoidrouting complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces horizontal metal tracking as a new dimension for routing, complementing the traditional vertical approach. This dimensional change provides additional routing pathways that bypass the constraints of high pin density, allowing complex connections to be established through horizontal routes rather than competing for limited vertical routing resources

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The horizontal metal tracks serve multiple functions: they provide primary routing pathways, enable vertical connections through integrated vias, and offer alternative routes for signal distribution. This multi-functionality reduces the overall complexity of the routing system by consolidating multiple routing tasks into a unified horizontal tracking infrastructure

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12610801B2Metallization process for an integrated circuit
Publication Date: 2026.04.21 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • US12610801B2 patent drawing
  • US12610801B2 patent drawing
  • US12610801B2 patent drawing

AI summary

The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via. The method further includes providing a planar dielectric material in contact with the first electrically conductive line, forming an opening in the planar dielectric material, filling the opening with a planar electrically conductive material, forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material, providing a hard mask comprising a set of parallel lines, and etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.